| Commit message (Expand) | Author | Age |
|---|
| * | Enable configuration of syscalls emulation and stop on exception. | Pavel Pisa | 2019-03-06 |
| * | Try the strict check of encoded instructions and relax break and other. | Pavel Pisa | 2019-03-05 |
| * | Dock to view coprocessor 0 and cop0 counter/comparator support. | Pavel Pisa | 2019-03-05 |
| * | Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM. | Pavel Pisa | 2019-03-04 |
| * | Implemented interrupt delivery and processing for serial port. | Pavel Pisa | 2019-03-04 |
| * | Implemented coprocessor 0 registers access and register EPC and Cause set by ... | Pavel Pisa | 2019-03-04 |
| * | Correct relative jumps range and adjust it for single core without delay-slot. | Pavel Pisa | 2019-02-24 |
| * | Add some more labels and clarify rs, rt, rd in execute stage. | Pavel Pisa | 2019-02-24 |
| * | Report forward and stall for branches and add forward to execution phase. | Pavel Pisa | 2019-02-18 |
| * | Visualize request to stall and stall in execution phase and exception sources. | Pavel Pisa | 2019-02-18 |
| * | Stall the pipeline even for branch which requires memory read as argument. | Pavel Pisa | 2019-02-18 |
| * | Do not update instruction in the decode stage when stalled. | Pavel Pisa | 2019-02-17 |
| * | Pass arithmetic exception trough pipeline and implement trap support and inst... | Pavel Pisa | 2019-02-17 |
| * | Implement EXT instruction used in GLIBC startup. | Pavel Pisa | 2019-02-15 |
| * | Core: move complex memory operation to own function and implement LWL, LWR, S... | Pavel Pisa | 2019-02-15 |
| * | Implement function to setup core C0 userlocal register. | Pavel Pisa | 2019-02-14 |
| * | Include simple serial port terminal and prepare empty peripheral dock. | Pavel Pisa | 2019-02-13 |
| * | Add signals and multiplexers for ALU inputs forwarding. | Pavel Pisa | 2019-02-12 |
| * | Display red background for instruction causing exception and skip HW breakpoi... | Pavel Pisa | 2019-02-11 |
| * | Basic "hardware" breakpoints support implemented. | Pavel Pisa | 2019-02-11 |
| * | Prepare core for "hardware" breakpoints support and add signals to follow sta... | Pavel Pisa | 2019-02-11 |
| * | Correct build for LLVM. | Fanda Vacek | 2019-02-09 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ... | Pavel Pisa | 2019-02-08 |
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG... | Pavel Pisa | 2019-02-08 |
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| * | Exception handlers require even PC of the jump or branch instruction before d... | Pavel Pisa | 2019-02-07 |
| * | Add address to emitted instruction to allow its use for branch address decoding. | Pavel Pisa | 2019-02-07 |
| * | Implemented basic infrastructure to handle exceptions. | Pavel Pisa | 2019-02-07 |
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Resolve some memory leaks found by Valgrind. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen... | Pavel Pisa | 2019-02-05 |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst... | Pavel Pisa | 2019-02-02 |
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 |
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| * | Correct processing of ORI, ANDI, XORI instructions which require zero-extende... | Pavel Pisa | 2019-01-31 |
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 |
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
