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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-18 15:49:34 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-18 15:49:34 +0100
commit3183ea5cd878570f4d6cef924369f0a4611a5c99 (patch)
tree652d9d15ec41df55204e0ff1a7e97908bdf77a60 /qtmips_machine/core.cpp
parent40ec86b16e297030f8fca02022dfa7a3e418b719 (diff)
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Visualize request to stall and stall in execution phase and exception sources.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_machine/core.cpp')
-rw-r--r--qtmips_machine/core.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 1b030d6..e6f0971 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -734,11 +734,11 @@ void CorePipelined::do_step(bool skip_break) {
printf("PC 0x%08lx\n", (unsigned long)dt_f.inst_addr);
#endif
- dt_d.stall = stall;
emit hu_stall_value(stall);
// Now process program counter (loop connections from decode stage)
if (!stall) {
+ dt_d.stall = false;
dt_f = fetch(skip_break);
if (handle_pc(dt_d)) {
dt_f.in_delay_slot = true;
@@ -753,6 +753,7 @@ void CorePipelined::do_step(bool skip_break) {
fetch(skip_break);
// clear decode latch (insert nope to execute stage)
dtDecodeInit(dt_d);
+ dt_d.stall = true;
// emit instruction_decoded(dt_d.inst, dt_d.inst_addr, dt_d.excause);
}
}