| Commit message (Expand) | Author | Age |
|---|
| * | Enable configuration of syscalls emulation and stop on exception. | Pavel Pisa | 2019-03-06 |
| * | Implemented coprocessor 0 registers access and register EPC and Cause set by ... | Pavel Pisa | 2019-03-04 |
| * | Correct relative jumps range and adjust it for single core without delay-slot. | Pavel Pisa | 2019-02-24 |
| * | Add some more labels and clarify rs, rt, rd in execute stage. | Pavel Pisa | 2019-02-24 |
| * | Report forward and stall for branches and add forward to execution phase. | Pavel Pisa | 2019-02-18 |
| * | Stall the pipeline even for branch which requires memory read as argument. | Pavel Pisa | 2019-02-18 |
| * | Core: move complex memory operation to own function and implement LWL, LWR, S... | Pavel Pisa | 2019-02-15 |
| * | Implement function to setup core C0 userlocal register. | Pavel Pisa | 2019-02-14 |
| * | Display red background for instruction causing exception and skip HW breakpoi... | Pavel Pisa | 2019-02-11 |
| * | Basic "hardware" breakpoints support implemented. | Pavel Pisa | 2019-02-11 |
| * | Prepare core for "hardware" breakpoints support and add signals to follow sta... | Pavel Pisa | 2019-02-11 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG... | Pavel Pisa | 2019-02-08 |
| * | Exception handlers require even PC of the jump or branch instruction before d... | Pavel Pisa | 2019-02-07 |
| * | Add address to emitted instruction to allow its use for branch address decoding. | Pavel Pisa | 2019-02-07 |
| * | Implemented basic infrastructure to handle exceptions. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst... | Pavel Pisa | 2019-02-02 |
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| * | Correct processing of ORI, ANDI, XORI instructions which require zero-extende... | Pavel Pisa | 2019-01-31 |
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| * | Add few more labels | Karel Kočí | 2018-05-24 |
| * | Add buses statis views | Karel Kočí | 2018-05-24 |
| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
| * | Add instruction view to single core | Karel Kočí | 2018-01-21 |
| * | Implement hazard unit | Karel Kočí | 2018-01-15 |
| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| * | Implement machine restart | Karel Kočí | 2018-01-05 |
| * | Allow delay slot disable for non-pipelined core | Karel Kočí | 2018-01-03 |
| * | Add trace-feth to qtmips_cli | Karel Kočí | 2018-01-03 |
| * | Use global includes in qtmips_machine | Karel Kočí | 2017-12-17 |
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
| * | Implement some store and load instructions | Karel Kočí | 2017-12-12 |
| * | Tiny cleanup | Karel Kočí | 2017-12-12 |
| * | Implement branch and jump instructions | Karel Kočí | 2017-12-12 |
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
| * | Implement some immediate arithmetic instructions | Karel Kočí | 2017-11-21 |
| * | Implement and test ADD | Karel Kočí | 2017-11-21 |
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| * | Initial commit | Karel Kočí | 2017-08-30 |
