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author | Karel Kočí <cynerd@email.cz> | 2017-12-12 21:18:45 +0100 |
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committer | Karel Kočí <cynerd@email.cz> | 2017-12-12 21:19:26 +0100 |
commit | 010194187d86041697f1e0e03edfc914940bd2ba (patch) | |
tree | 9492ed00912fbff774c70c18f0b991dd41dcacb1 /qtmips_machine/core.h | |
parent | ee64b00aa89f1ab4963607468dd42d77d7ef3f76 (diff) | |
download | qtmips-010194187d86041697f1e0e03edfc914940bd2ba.tar.gz qtmips-010194187d86041697f1e0e03edfc914940bd2ba.tar.bz2 qtmips-010194187d86041697f1e0e03edfc914940bd2ba.zip |
Implement some store and load instructions
Diffstat (limited to 'qtmips_machine/core.h')
-rw-r--r-- | qtmips_machine/core.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h index e583235..07933ab 100644 --- a/qtmips_machine/core.h +++ b/qtmips_machine/core.h @@ -26,24 +26,29 @@ protected: }; struct dtDecode { Instruction inst; - bool mem2reg; // Write memory output to register (instead alu output) + bool memread; // If memory should be read bool memwrite; // If memory should write input bool alusrc; // If second value to alu is immediate value (rt used otherwise) bool regd; // If rd is used (otherwise rt is used for write target) bool regwrite; // If output should be written back to register (which one depends on regd) enum AluOp aluop; // Decoded ALU operation + enum MemoryAccess::AccessControl memctl; // Decoded memory access type std::uint32_t val_rs; // Value from register rs std::uint32_t val_rt; // Value from register rt }; struct dtExecute { + bool memread; + bool memwrite; bool regwrite; + enum MemoryAccess::AccessControl memctl; + std::uint32_t val_rt; std::uint8_t rwrite; // Writeback register (multiplexed between rt and rd according to regd) std::uint32_t alu_val; // Result of ALU execution }; struct dtMemory { bool regwrite; std::uint8_t rwrite; - std::uint32_t alu_val; + std::uint32_t towrite_val; }; struct dtFetch fetch(); |