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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-01-31 11:02:03 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-01-31 11:02:03 +0100
commiteab6cf4fc5720b330ba89c38e9e6119a8a6fabfa (patch)
treee706c645c9ee51b1a9fcbf15fee6bda870d1cd54 /qtmips_machine/core.h
parent6a6bd48da1f09be7dc7c53f13393b07889eea364 (diff)
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Initial support for JAL.
The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_machine/core.h')
-rw-r--r--qtmips_machine/core.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h
index 625fe29..66eb1e6 100644
--- a/qtmips_machine/core.h
+++ b/qtmips_machine/core.h
@@ -49,6 +49,7 @@ signals:
void decode_rs_num_value(std::uint32_t);
void decode_rt_num_value(std::uint32_t);
void decode_rd_num_value(std::uint32_t);
+ void decode_regd31_value(std::uint32_t);
void execute_alu_value(std::uint32_t);
void execute_reg1_value(std::uint32_t);
void execute_reg2_value(std::uint32_t);
@@ -83,6 +84,7 @@ protected:
struct dtFetch {
Instruction inst; // Loaded instruction
+ uint32_t inst_addr; // Address of instruction
};
struct dtDecode {
Instruction inst;
@@ -90,6 +92,7 @@ protected:
bool memwrite; // If memory should write input
bool alusrc; // If second value to alu is immediate value (rt used otherwise)
bool regd; // If rd is used (otherwise rt is used for write target)
+ bool regd31; // Use R31 as destionation for JAL
bool regwrite; // If output should be written back to register (which one depends on regd)
enum AluOp aluop; // Decoded ALU operation
enum MemoryAccess::AccessControl memctl; // Decoded memory access type