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path: root/qtmips_machine/core.h
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* Enable configuration of syscalls emulation and stop on exception.Pavel Pisa2019-03-06
* Implemented coprocessor 0 registers access and register EPC and Cause set by ...Pavel Pisa2019-03-04
* Correct relative jumps range and adjust it for single core without delay-slot.Pavel Pisa2019-02-24
* Add some more labels and clarify rs, rt, rd in execute stage.Pavel Pisa2019-02-24
* Report forward and stall for branches and add forward to execution phase.Pavel Pisa2019-02-18
* Stall the pipeline even for branch which requires memory read as argument.Pavel Pisa2019-02-18
* Core: move complex memory operation to own function and implement LWL, LWR, S...Pavel Pisa2019-02-15
* Implement function to setup core C0 userlocal register.Pavel Pisa2019-02-14
* Display red background for instruction causing exception and skip HW breakpoi...Pavel Pisa2019-02-11
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
* Prepare core for "hardware" breakpoints support and add signals to follow sta...Pavel Pisa2019-02-11
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG...Pavel Pisa2019-02-08
* Exception handlers require even PC of the jump or branch instruction before d...Pavel Pisa2019-02-07
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst...Pavel Pisa2019-02-02
* Initial support for JAL.Pavel Pisa2019-01-31
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
* Correct processing of ORI, ANDI, XORI instructions which require zero-extende...Pavel Pisa2019-01-31
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
* Add few more labelsKarel Kočí2018-05-24
* Add buses statis viewsKarel Kočí2018-05-24
* Implement sync for memoryKarel Kočí2018-04-08
* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
* Add instruction view to single coreKarel Kočí2018-01-21
* Implement hazard unitKarel Kočí2018-01-15
* Allow instruction trace from any stageKarel Kočí2018-01-11
* Implement machine restartKarel Kočí2018-01-05
* Allow delay slot disable for non-pipelined coreKarel Kočí2018-01-03
* Add trace-feth to qtmips_cliKarel Kočí2018-01-03
* Use global includes in qtmips_machineKarel Kočí2017-12-17
* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
* Implement some store and load instructionsKarel Kočí2017-12-12
* Tiny cleanupKarel Kočí2017-12-12
* Implement branch and jump instructionsKarel Kočí2017-12-12
* Test pipelined coreKarel Kočí2017-11-25
* Implement some immediate arithmetic instructionsKarel Kočí2017-11-21
* Implement and test ADDKarel Kočí2017-11-21
* Another huge pile of work for about two monthsKarel Kočí2017-11-19
* Initial commitKarel Kočí2017-08-30