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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows to easier identify unused pipeline stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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When instructions are visualized then it is even more
misleading to keep old instruction in decode phase delay buffer.
The single cycle core with delay slot is upgraded
to the variant with fetch and execute phases.
This way the structure is logical and delay slot
has purpose.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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exception.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Setting bits 16 to 31 to 1 is incorrect, offset is shift
by two so bit 16 can be zero for jumps in range -64k to -128k.
Adjust relative offsets to compute target address same, as if there
is delay slot, for CPU variant without delay slot.
This allows to use same/standard MIPS assembler for mode
without delay slots.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows simple visual compare of rs and rt in execution stage
with register number to be written in memory and write-back stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This type of the hazard doe not cause problems in the simulator
because processing of memory stage is already finished
at time when PC handling is started but it would cause
problems in real hardware where PC handling is processed
in parallel to memory load.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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SWL, SWR.
The move makes basic memory stage processing more readable.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well.
But other signals are left intact, it is duty of memory stage
to discard effect of instruction causing interrupt.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It works like real inserted breakpoint on hardware.
Breakpoint has to be removed to allow code continue
because else instruction is refetch and breakpoint
triggers again. The single step function should
resolve temporal masking of the breakpoint.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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BGEZALL.
GCC generates these opcodes for default compilation mode.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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delay slot.
When exception occurs at instruction in delay slot, the address
of branch/delay instruction is stored to EPC instead of address
of instruction causing the exception. So that address has
to be delivered to exception handling object.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The new Qt5 syntax is used to create connections because
old syntax does not work with multiple arguments for some
unresolved reason.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Memory stage is chosen to be exception commit stage.
Instructions flow postponed and stages holding following
instructions are cleaned. Processing of syscall at decode
stage as jump to the handler would be better solution
in real hardware but for future emulated syscalls
it is better to reach consistent state of registers.
Memory access caused exceptions would require cleanup
even in real hardware.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows to specify requirement for RS and RD on instruction
basis even for T_R / ALU instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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instructions.
The previous code worked by chance only because decode has been fully
processed including forwarding from M and W before PC processing
started. But in real hardware the PC processing runs in parallel
with ALU and cannot read its results in the same cycle.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The JR, BEQ, BNE are most probably incorrect still.
There is missing forwarding for pipelined execution.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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zero-extended immediate.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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In reality this internally allows us to see stages even it we are not
using pipelining but that is hidden from outside simply to not confuse
user.
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