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path: root/qtmips_machine/core.cpp
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* Set gray background to stalled instructions/idled stages.Pavel Pisa2019-03-31
| | | | | | This allows to easier identify unused pipeline stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Change single cycle core with delay slot to use separate fetch stage.Pavel Pisa2019-03-26
| | | | | | | | | | | | When instructions are visualized then it is even more misleading to keep old instruction in decode phase delay buffer. The single cycle core with delay slot is upgraded to the variant with fetch and execute phases. This way the structure is logical and delay slot has purpose. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Highlight instructions passing through the pipeline stages.Pavel Pisa2019-03-25
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct use of uninitialized dt_d.num_rd and delete reported by valgrind.Pavel Pisa2019-03-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Enable configuration of syscalls emulation and stop on exception.Pavel Pisa2019-03-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Try the strict check of encoded instructions and relax break and other.Pavel Pisa2019-03-05
| | | | | | | Some instructions can have fields to be used by operating system or for error reporting by user. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Dock to view coprocessor 0 and cop0 counter/comparator support.Pavel Pisa2019-03-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM.Pavel Pisa2019-03-04
| | | | | | | Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented interrupt delivery and processing for serial port.Pavel Pisa2019-03-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented coprocessor 0 registers access and register EPC and Cause set by ↵Pavel Pisa2019-03-04
| | | | | | exception. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct relative jumps range and adjust it for single core without delay-slot.Pavel Pisa2019-02-24
| | | | | | | | | | | | Setting bits 16 to 31 to 1 is incorrect, offset is shift by two so bit 16 can be zero for jumps in range -64k to -128k. Adjust relative offsets to compute target address same, as if there is delay slot, for CPU variant without delay slot. This allows to use same/standard MIPS assembler for mode without delay slots. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add some more labels and clarify rs, rt, rd in execute stage.Pavel Pisa2019-02-24
| | | | | | | This allows simple visual compare of rs and rt in execution stage with register number to be written in memory and write-back stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Report forward and stall for branches and add forward to execution phase.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Visualize request to stall and stall in execution phase and exception sources.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Stall the pipeline even for branch which requires memory read as argument.Pavel Pisa2019-02-18
| | | | | | | | | | This type of the hazard doe not cause problems in the simulator because processing of memory stage is already finished at time when PC handling is started but it would cause problems in real hardware where PC handling is processed in parallel to memory load. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not update instruction in the decode stage when stalled.Pavel Pisa2019-02-17
| | | | | | | Decode dt_d represents next input to execute stage not state of decode stage at this moment. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Pass arithmetic exception trough pipeline and implement trap support and ↵Pavel Pisa2019-02-17
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
| | | | | | It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Core: move complex memory operation to own function and implement LWL, LWR, ↵Pavel Pisa2019-02-15
| | | | | | | | SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement function to setup core C0 userlocal register.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include simple serial port terminal and prepare empty peripheral dock.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add signals and multiplexers for ALU inputs forwarding.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display red background for instruction causing exception and skip HW ↵Pavel Pisa2019-02-11
| | | | | | | | | | breakpoint for first cycle after resume. Instruction for stage is updated when given stage is flushed as well. But other signals are left intact, it is duty of memory stage to discard effect of instruction causing interrupt. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
| | | | | | | | | | It works like real inserted breakpoint on hardware. Breakpoint has to be removed to allow code continue because else instruction is refetch and breakpoint triggers again. The single step function should resolve temporal masking of the breakpoint. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Prepare core for "hardware" breakpoints support and add signals to follow ↵Pavel Pisa2019-02-11
| | | | | | stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct build for LLVM.Fanda Vacek2019-02-09
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* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ↵Pavel Pisa2019-02-08
| | | | | | | | | | opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Exception handlers require even PC of the jump or branch instruction before ↵Pavel Pisa2019-02-07
| | | | | | | | | | | delay slot. When exception occurs at instruction in delay slot, the address of branch/delay instruction is stored to EPC instead of address of instruction causing the exception. So that address has to be delivered to exception handling object. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
| | | | | | | | The new Qt5 syntax is used to create connections because old syntax does not work with multiple arguments for some unresolved reason. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented base for exception handling.Pavel Pisa2019-02-06
| | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵Pavel Pisa2019-02-05
| | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
| | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Take into account actual requirements for rs, rt and rd write for individual ↵Pavel Pisa2019-02-04
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
| | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include support for JALR support.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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