| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Change single cycle core with delay slot to use separate fetch stage. | Pavel Pisa | 2019-03-26 |
| | | | | | | | | | | | | | When instructions are visualized then it is even more misleading to keep old instruction in decode phase delay buffer. The single cycle core with delay slot is upgraded to the variant with fetch and execute phases. This way the structure is logical and delay slot has purpose. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct write through spelling. Reported by Richard Susta. | Pavel Pisa | 2019-03-25 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Fix LB and LH sign extension and LH/SH mask calculation. | Pavel Pisa | 2019-03-13 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Added test for LWR, LWL, SWR and SWL instructions. | Pavel Pisa | 2019-02-21 |
| | | | | | | | | The reference data has been obtained by running application under userspace MIPS QEMU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Distinguish between write-through cache with allocate and update only if hit. | Pavel Pisa | 2019-02-20 |
| | | | | | | | | Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include test for BGEZ, BGTZ, BLEZ, BLTZ, BEQ and BNE. | Pavel Pisa | 2019-02-05 |
| | | | | | | | | This complex test check for correct behavior for -1, 0 and 1 values. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include more complex insert-sort test which checks memory and cache. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Simplify core test by use of common function to run test machine. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include test for jump and link processing. | Pavel Pisa | 2019-02-02 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add test for forwarding in ALU operations. | Pavel Pisa | 2019-02-02 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement LUI | Karel Kočí | 2018-04-08 |
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| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
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| * | Fix signextend in core | Karel Kočí | 2018-02-14 |
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| * | Fix SRA and SRAV instructions | Karel Kočí | 2018-01-15 |
| | | | | | | | This implementation is correct one but there is no guarantee that it will work with all compilers so we should always check on given platform that tests pass (and potentially fix it). | ||
| * | Allow delay slot disable for non-pipelined core | Karel Kočí | 2018-01-03 |
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| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
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| * | Fix test for JR | Karel Kočí | 2017-12-12 |
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| * | Implement some store and load instructions | Karel Kočí | 2017-12-12 |
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| * | Implement branch and jump instructions | Karel Kočí | 2017-12-12 |
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| * | Add crude implementation of MOV* instructions | Karel Kočí | 2017-11-25 |
| | | | | | I don't like how it's implemented but I have no other idea atm. | ||
| * | Implement instructions for moving from and to HI and LO registers | Karel Kočí | 2017-11-25 |
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| * | Test pipelined core | Karel Kočí | 2017-11-25 |
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| * | Implement some logical operations | Karel Kočí | 2017-11-21 |
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| * | Implement some immediate arithmetic instructions | Karel Kočí | 2017-11-21 |
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| * | Implement tests for few more arithmetic instructions | Karel Kočí | 2017-11-21 |
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| * | Implement and test ADD | Karel Kočí | 2017-11-21 |
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| * | Add possibility to compare memory and registers state | Karel Kočí | 2017-11-21 |
| | | | | | | | For core testing we want to compare whole memory and registers. Registers are pretty simple but in case of memory it is some what more complicated and required its own tests to be sure that it works. | ||
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| | | | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression. | ||
| * | Just something I had stagged | Karel Kočí | 2017-11-19 |
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