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author | Karel Kočí <cynerd@email.cz> | 2017-11-21 19:48:51 +0100 |
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committer | Karel Kočí <cynerd@email.cz> | 2017-11-21 19:48:51 +0100 |
commit | 499a88621d12ff0cdcba1f8c796b7031d6adc649 (patch) | |
tree | c050b5224c896b3e14d74866473aef9c2a5e9b69 /qtmips_machine/tests/testcore.cpp | |
parent | 68f2af6801756980ec53347c0acb7fcc292f7939 (diff) | |
download | qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.tar.gz qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.tar.bz2 qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.zip |
Add possibility to compare memory and registers state
For core testing we want to compare whole memory and registers.
Registers are pretty simple but in case of memory it is some what more
complicated and required its own tests to be sure that it works.
Diffstat (limited to 'qtmips_machine/tests/testcore.cpp')
-rw-r--r-- | qtmips_machine/tests/testcore.cpp | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index bbf8086..33bf07e 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -2,28 +2,43 @@ #include "core.h" void MachineTests::core_regs_data() { - /* QTest::addColumn<Instruction>("i"); QTest::addColumn<Registers>("init"); QTest::addColumn<Registers>("res"); // Test arithmetic instructions { - Registers regs_init(); + Registers regs_init; regs_init.write_gp(24, 12); regs_init.write_gp(25, 24); - Registers regs_res(®s_init); + Registers regs_res(regs_init); regs_res.write_gp(26, 36); QTest::newRow("ADD") << Instruction(0, 24, 25, 26, 0, 32) \ << regs_init \ << regs_res; } - */ // TODO test other operations } void MachineTests::core_regs() { + QTest::addColumn<Instruction>("i"); + QTest::addColumn<Registers>("init"); + QTest::addColumn<Registers>("res"); + QFETCH(Instruction, i); + QFETCH(Registers, init); + QFETCH(Registers, res); + + Memory mem; // Just memory (it shouldn't be used here except instruction) + mem.write_word(res.read_pc(), i.data()); // Store single instruction (anything else should be 0 so NOP effectively) + + // Test on non-piplined + Memory mem_single(mem); // Create memory copy + CoreSingle core_single(&init, &mem_single); + core_single.step(); // Single step should be enought as this is risc without pipeline + //QCOMPARE(init, res); // After doing changes from initial state this should be same state as in case of passed expected result + QCOMPARE(mem, mem_single); // There should be no change in memory + // TODO on pipelined core } void MachineTests::core_mem_data() { |