Change single cycle core with delay slot to use separate fetch stage.

When instructions are visualized then it is even more
misleading to keep old instruction in decode phase delay buffer.

The single cycle core with delay slot is upgraded
to the variant with fetch and execute phases.
This way the structure is logical and delay slot
has purpose.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

1 files changed, 4 insertions, 0 deletions

diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp
index 68da14c..7ba185d 100644
--- a/qtmips_machine/tests/testcore.cpp
+++ b/qtmips_machine/tests/testcore.cpp
@@ -230,7 +230,9 @@ void MachineTests::singlecore_regs() {
 
     CoreSingle core(&init, &mem_used, &mem_used, true);
     core.step(); // Single step should be enought as this is risc without pipeline
+    core.step();
 
+    res.pc_inc();
     res.pc_inc(); // We did single step	so increment program counter accordingly
     QCOMPARE(init, res); // After doing changes from initial state this should be same state as in case of passed expected result
     QCOMPARE(mem, mem_used); // There should be no change in memory
@@ -444,8 +446,10 @@ void MachineTests::singlecore_mem() {
 
     CoreSingle core(&regs_init, &mem_init, &mem_init, true);
     core.step();
+    core.step();
 
     regs_res.pc_inc();
+    regs_res.pc_inc();
     QCOMPARE(regs_init, regs_res);
     QCOMPARE(mem_init, mem_res);
 }