aboutsummaryrefslogtreecommitdiff
path: root/qtmips_machine/instruction.h
Commit message (Collapse)AuthorAge
* Minimal prototype of integrated assembler.Pavel Pisa2019-07-01
| | | | | | | The labels are parsed and stored into symbol table but expressions dependent on symbols values are not evaluated. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Complete revamp of disassembler and assembler arguments processing.Pavel Pisa2019-03-05
| | | | | | | | | | | | | | | | | | | | | Instructions description in instruction.cpp has been pragmatically augmented by tool based on Python MIPS simulator, hazards analyzer https://github.com/ppisa/apo-simarch That code has been originally distilled from from GNU binutils sources. Implementation is now inline with my original proposal Previous solution gets untenable with more complex instructions and its complexity would grow extremely. MIPS instruction set with coprocessor instructions which use sel field, rd used as index, rt as destination and other peculiarities in newer versions cannot be processed based on basic CPU control signals. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented coprocessor 0 registers access and register EPC and Cause set by ↵Pavel Pisa2019-03-04
| | | | | | exception. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make memory and program listing editable.Pavel Pisa2019-02-12
| | | | | | Instruction parsing is rough and does not support branch offset computation. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented base for exception handling.Pavel Pisa2019-02-06
| | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵Pavel Pisa2019-02-05
| | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
| | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
| | | | THere are exceptions when we care about forwarding and when we don't.
* Allow instruction trace from any stageKarel Kočí2018-01-11
| | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user.
* Initial implementation of reverse instruction conversionKarel Kočí2018-01-03
| | | | | | This is rude implementation. We always print all fields. In future we should add flags to set what fields should be hidden on per instruction bases.
* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
|
* Test pipelined coreKarel Kočí2017-11-25
|
* Implement tests for few more arithmetic instructionsKarel Kočí2017-11-21
|
* Add possibility to compare memory and registers stateKarel Kočí2017-11-21
| | | | | | For core testing we want to compare whole memory and registers. Registers are pretty simple but in case of memory it is some what more complicated and required its own tests to be sure that it works.
* Another huge pile of work for about two monthsKarel Kočí2017-11-19
| | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression.
* Add some more instructions to be decoded and arithmetic I testKarel Kočí2017-09-05
|
* Use QString and QVector instead of std ones and moreKarel Kočí2017-09-02
|
* Some to_string_hex cleanupsKarel Kočí2017-08-30
|
* Initial commitKarel Kočí2017-08-30
Adding work done so far.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 22:27:29 +0000