Implemented base for exception handling.

Memory stage is chosen to be exception commit stage.

Instructions flow postponed and stages holding following
instructions are cleaned. Processing of syscall at decode
stage as jump to the handler would be better solution
in real hardware but for future emulated syscalls
it is better to reach consistent state of registers.
Memory access caused exceptions would require cleanup
even in real hardware.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

1 files changed, 2 insertions, 0 deletions

diff --git a/qtmips_machine/instruction.h b/qtmips_machine/instruction.h
index a8779f5..b26d9ac 100644
--- a/qtmips_machine/instruction.h
+++ b/qtmips_machine/instruction.h
@@ -67,6 +67,7 @@ enum InstructionFlags {
     IMF_JUMP       = 1L<<19,
     IMF_BJ_NOT     = 1L<<20,
     IMF_BGTZ_BLEZ  = 1L<<21,
+    IMF_EXCEPTION  = 1L<<22,
 };
 
 class Instruction {
@@ -98,6 +99,7 @@ public:
     enum InstructionFlags flags() const;
     enum AluOp alu_op() const;
     enum AccessControl mem_ctl() const;
+    enum ExceptionCause encoded_exception() const;
 
     void flags_alu_op_mem_ctl(enum InstructionFlags &flags,
                   enum AluOp &alu_op, enum AccessControl &mem_ctl) const;