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path: root/qtmips_machine/core.cpp
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* Display red background for instruction causing exception and skip HW breakpoi...Pavel Pisa2019-02-11
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
* Prepare core for "hardware" breakpoints support and add signals to follow sta...Pavel Pisa2019-02-11
* Correct build for LLVM.Fanda Vacek2019-02-09
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ...Pavel Pisa2019-02-08
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG...Pavel Pisa2019-02-08
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
* Exception handlers require even PC of the jump or branch instruction before d...Pavel Pisa2019-02-07
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen...Pavel Pisa2019-02-05
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst...Pavel Pisa2019-02-02
* Include support for JALR support.Pavel Pisa2019-01-31
* Initial support for JAL.Pavel Pisa2019-01-31
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
* Correct processing of ORI, ANDI, XORI instructions which require zero-extende...Pavel Pisa2019-01-31
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
* Correct hazards processing.Pavel Pisa2019-01-30
* Add few more labelsKarel Kočí2018-05-24
* Add buses statis viewsKarel Kočí2018-05-24
* Fix load and store instructionsKarel Kočí2018-05-02
* Implement LUIKarel Kočí2018-04-08
* Implement sync for memoryKarel Kočí2018-04-08
* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
* Fix signextend in coreKarel Kočí2018-02-14
* Add instruction view to single coreKarel Kočí2018-01-21
* Cleanup some todos in codeKarel Kočí2018-01-15
* Implement hazard unitKarel Kočí2018-01-15
* Allow instruction trace from any stageKarel Kočí2018-01-11
* Implement machine restartKarel Kočí2018-01-05
* Allow delay slot disable for non-pipelined coreKarel Kočí2018-01-03
* Add trace-feth to qtmips_cliKarel Kočí2018-01-03