| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵ | Pavel Pisa | 2019-02-05 |
| | | | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Make instruction to text conversion more generic. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Setup initial PC according executable entry form ELF file if it is non zero. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Define uncached region in range from 0xf0000000 to 0xffffffff. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Take into account actual requirements for rs, rt and rd write for individual ↵ | Pavel Pisa | 2019-02-04 |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| | | | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include more complex insert-sort test which checks memory and cache. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Simplify core test by use of common function to run test machine. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct write-back cache behavior. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct memory view updates for uncached and write-through case. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵ | Pavel Pisa | 2019-02-02 |
| | | | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include test for jump and link processing. | Pavel Pisa | 2019-02-02 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add test for forwarding in ALU operations. | Pavel Pisa | 2019-02-02 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct ALU test for SUB exception. | Pavel Pisa | 2019-02-02 |
| | | | | | | | | | | | | | The operation 3 - 4 = 1 is legal integer arithmetic operation. Changed to 0x80000003 - 4 = 0x7fffffff 2147483651 - 4 = 2147483647 which overflows. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| | | | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct signed arithmetic overflow exception. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct processing of ORI, ANDI, XORI instructions which require ↵ | Pavel Pisa | 2019-01-31 |
| | | | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct hazards processing. | Pavel Pisa | 2019-01-30 |
| | | | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Specify rpath during linking to find qtmips_machine library without install. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Hide some values that shouldn't been visible in no pipelined version | Karel Kočí | 2018-06-20 |
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| * | Fix value position for non-pipelined core | Karel Kočí | 2018-05-24 |
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| * | Add few more labels | Karel Kočí | 2018-05-24 |
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| * | Add few additional labels | Karel Kočí | 2018-05-24 |
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| * | Add buses statis views | Karel Kočí | 2018-05-24 |
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| * | Add cache view renderer | Karel Kočí | 2018-05-23 |
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| * | Ignore hazard unit for now | Karel Kočí | 2018-05-23 |
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| * | Add cache statistics | Karel Kočí | 2018-05-23 |
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| * | Fix load and store instructions | Karel Kočí | 2018-05-02 |
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| * | Initial implementation of cache view | Karel Kočí | 2018-04-17 |
| | | | | | It needs some more work to look nice but it already works. | ||
| * | Drop unneeded parameter from CoreViewScene constructor | Karel Kočí | 2018-04-17 |
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| * | Fix angle scroll speed | Karel Kočí | 2018-04-17 |
| | | | | | | I finally manage to make device to report as angle scroll device. And it was too fast scroll so I make it solver. It is now some what acceptable. | ||
| * | Store memory and program view address position | Karel Kočí | 2018-04-17 |
| | | | | | | | This reloads memoryview with same base address as it was closed with. It somewhat works but with program view it seems to be buggy and shifts stuff down. But let's say that it's good enough for now. | ||
| * | When changing focus load it back to edit field in memoryview | Karel Kočí | 2018-04-15 |
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| * | Add 2x speed | Karel Kočí | 2018-04-15 |
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| * | Disable memory protection configuration fields for now | Karel Kočí | 2018-04-15 |
| | | | | | | Memory protection is not feature that is strictly required. Because of that it's implementation has lower priority. | ||
| * | Change presets | Karel Kočí | 2018-04-15 |
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| * | Rename CoreView to GraphicsView | Karel Kočí | 2018-04-15 |
| | | | | | | This generalizes CoreView to be used with other parts of the project too. | ||
| * | Add cache dock | Karel Kočí | 2018-04-15 |
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| * | Fix coverview memory cache | Karel Kočí | 2018-04-15 |
| | | | | | Text was always rendered. | ||
| * | Show cache statistics in Memory block in coreview | Karel Kočí | 2018-04-15 |
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index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
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