Add few more labels

3 files changed, 75 insertions, 25 deletions

diff --git a/qtmips_gui/coreview.cpp b/qtmips_gui/coreview.cpp
index d91def6..2e5bb82 100644
--- a/qtmips_gui/coreview.cpp
+++ b/qtmips_gui/coreview.cpp
@@ -19,7 +19,10 @@
         NEW(InstructionView, VAR, X, Y); \
         connect(machine->core(), SIGNAL(SIG), VAR, SLOT(instruction_update(const machine::Instruction&))); \
     } while(false)
-#define NEW_V(X, Y, ...) NEW(Value, val, X, Y, __VA_ARGS__)
+#define NEW_V(X, Y, SIG, ...) do { \
+        NEW(Value, val, X, Y, __VA_ARGS__); \
+        connect(machine->core(), SIGNAL(SIG(std::uint32_t)), val, SLOT(value_update(std::uint32_t))); \
+    } while(false)
 
 CoreViewScene::CoreViewScene(machine::QtMipsMachine *machine) : QGraphicsScene() {
     setSceneRect(0, 0, SC_WIDTH, SC_HEIGHT);
@@ -106,34 +109,42 @@ CoreViewScene::CoreViewScene(machine::QtMipsMachine *machine) : QGraphicsScene()
     new_label("RegDest", 300, 138);
     new_label("Branch", 300, 145);
 
+    // Fetch stage values
+    NEW_V(25, 440, fetch_branch_value, false, 1);
     // Decode stage values
-    NEW_V(200, 200); // Instruction
-    connect(machine->core(), SIGNAL(decode_instruction_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(360, 250); // Register output 1
-    connect(machine->core(), SIGNAL(decode_reg1_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(360, 270); // Register output 2
-    connect(machine->core(), SIGNAL(decode_reg2_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(335, 415); // Sign extended immediate value
-    connect(machine->core(), SIGNAL(decode_immediate_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
+    NEW_V(200, 200, decode_instruction_value); // Instruction
+    NEW_V(360, 250, decode_reg1_value); // Register output 1
+    NEW_V(360, 270, decode_reg2_value); // Register output 2
+    NEW_V(335, 415, decode_immediate_value); // Sign extended immediate value
+    NEW_V(360, 105, decode_regw_value, false, 1); // RegWrite
+    NEW_V(370, 113, decode_memtoreg_value, false, 1);
+    NEW_V(360, 120, decode_memwrite_value, false, 1);
+    NEW_V(370, 127, decode_memread_value, false, 1);
+    NEW_V(360, 140, decode_alusrc_value, false, 1);
+    NEW_V(370, 148, decode_regdest_value, false, 1);
     // Execute stage
-    NEW_V(430, 250); // Register 1
-    connect(machine->core(), SIGNAL(execute_reg1_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(420, 310, true); // Register 2
-    connect(machine->core(), SIGNAL(execute_reg2_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(520, 280, true); // Alu output
-    connect(machine->core(), SIGNAL(execute_alu_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(430, 415); // Immediate value
-    connect(machine->core(), SIGNAL(execute_immediate_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
+    NEW_V(430, 250, execute_reg1_value); // Register 1
+    NEW_V(420, 310, execute_reg2_value, true); // Register 2
+    NEW_V(520, 280, execute_alu_value, true); // Alu output
+    NEW_V(430, 415, execute_immediate_value); // Immediate value
+    NEW_V(460, 105, execute_regw_value, false, 1); // RegWrite
+    NEW_V(470, 113, execute_memtoreg_value, false, 1);
+    NEW_V(460, 120, execute_memwrite_value, false, 1);
+    NEW_V(470, 127, execute_memread_value, false, 1);
+    NEW_V(470, 127, execute_memread_value, false, 1);
+    NEW_V(455, 290, execute_alusrc_value, false, 1);
+    NEW_V(410, 190, execute_regdest_value, false, 1);
     // Memory stage
-    NEW_V(560, 275, true); // Alu output
-    connect(machine->core(), SIGNAL(memory_alu_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(560, 345, true); // rt
-    connect(machine->core(), SIGNAL(memory_rt_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
-    NEW_V(650, 290, true); // Memory output
-    connect(machine->core(), SIGNAL(memory_mem_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
+    NEW_V(560, 275,  memory_alu_value, true); // Alu output
+    NEW_V(560, 345, memory_rt_value, true); // rt
+    NEW_V(650, 290, memory_mem_value, true); // Memory output
+    NEW_V(560, 105, execute_regw_value, false, 1); // RegWrite
+    NEW_V(570, 113, execute_memtoreg_value, false, 1);
+    NEW_V(630, 220, memory_memwrite_value, false, 1);
+    NEW_V(620, 220, memory_memread_value, false, 1);
     // Write back stage
-    NEW_V(710, 330, true); // Write back value
-    connect(machine->core(), SIGNAL(writeback_value(std::uint32_t)), val, SLOT(value_update(std::uint32_t)));
+    NEW_V(710, 330, writeback_value, true); // Write back value
+    NEW_V(460, 45, writeback_regw_value, false, 1);
 
 
     connect(regs, SIGNAL(open_registers()), this, SIGNAL(request_registers()));
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 481190b..49149f7 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -133,6 +133,12 @@ struct Core::dtDecode Core::decode(const struct dtFetch &dt) {
     emit decode_reg1_value(val_rs);
     emit decode_reg2_value(val_rt);
     emit decode_immediate_value(sign_extend(dt.inst.immediate()));
+    emit decode_regw_value((bool)(dec.flags & DM_REGWRITE));
+    emit decode_memtoreg_value((bool)(dec.flags & DM_MEMREAD));
+    emit decode_memwrite_value((bool)(dec.flags & DM_MEMWRITE));
+    emit decode_memread_value((bool)(dec.flags & DM_MEMREAD));
+    emit decode_alusrc_value((bool)(dec.flags & DM_ALUSRC));
+    emit decode_regdest_value((bool)(dec.flags & DM_REGD));
 
     return {
         .inst = dt.inst,
@@ -166,6 +172,12 @@ struct Core::dtExecute Core::execute(const struct dtDecode &dt) {
     emit execute_reg1_value(dt.val_rs);
     emit execute_reg2_value(dt.val_rt);
     emit execute_immediate_value(sign_extend(dt.inst.immediate()));
+    emit execute_regw_value(dt.regwrite);
+    emit execute_memtoreg_value(dt.memread);
+    emit execute_memread_value(dt.memread);
+    emit execute_memwrite_value(dt.memwrite);
+    emit execute_alusrc_value(dt.alusrc);
+    emit execute_regdest_value(dt.regd);
 
     return {
         .inst = dt.inst,
@@ -191,6 +203,10 @@ struct Core::dtMemory Core::memory(const struct dtExecute &dt) {
     emit memory_alu_value(dt.alu_val);
     emit memory_rt_value(dt.val_rt);
     emit memory_mem_value(dt.memread ? towrite_val : 0);
+    emit memory_regw_value(dt.regwrite);
+    emit memory_memtoreg_value(dt.memread);
+    emit memory_memread_value(dt.memread);
+    emit memory_memwrite_value(dt.memwrite);
 
     return {
         .inst = dt.inst,
@@ -203,6 +219,7 @@ struct Core::dtMemory Core::memory(const struct dtExecute &dt) {
 void Core::writeback(const struct dtMemory &dt) {
     emit instruction_writeback(dt.inst);
     emit writeback_value(dt.towrite_val);
+    emit writeback_regw_value(dt.regwrite);
     if (dt.regwrite)
         regs->write_gp(dt.rwrite, dt.towrite_val);
 }
@@ -218,6 +235,7 @@ void Core::handle_pc(const struct dtDecode &dt) {
     case 0: // JR (JALR)
         if (dt.inst.funct() == ALU_OP_JR || dt.inst.funct() == ALU_OP_JALR) {
             regs->pc_abs_jmp(dt.val_rs);
+            emit fetch_branch_value(true);
             return;
         }
         break;
@@ -238,6 +256,7 @@ void Core::handle_pc(const struct dtDecode &dt) {
     case 2: // J
     case 3: // JAL
         regs->pc_abs_jmp_28(dt.inst.address() << 2);
+        emit fetch_branch_value(true);
         return;
     case 4: // BEQ
         branch = dt.val_rs == dt.val_rt;
@@ -253,6 +272,8 @@ void Core::handle_pc(const struct dtDecode &dt) {
         break;
     }
 
+    emit fetch_branch_value(branch);
+
     if (branch)
         regs->pc_jmp((std::int32_t)(((dt.inst.immediate() & 0x8000) ? 0xFFFF0000 : 0) | (dt.inst.immediate() << 2)));
     else
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h
index 64fe409..b368b3b 100644
--- a/qtmips_machine/core.h
+++ b/qtmips_machine/core.h
@@ -29,18 +29,36 @@ signals:
     void instruction_writeback(const machine::Instruction &inst);
     void instruction_program_counter(const machine::Instruction &inst);
 
+    void fetch_branch_value(std::uint32_t);
     void decode_instruction_value(std::uint32_t);
     void decode_reg1_value(std::uint32_t);
     void decode_reg2_value(std::uint32_t);
     void decode_immediate_value(std::uint32_t);
+    void decode_regw_value(std::uint32_t);
+    void decode_memtoreg_value(std::uint32_t);
+    void decode_memwrite_value(std::uint32_t);
+    void decode_memread_value(std::uint32_t);
+    void decode_alusrc_value(std::uint32_t);
+    void decode_regdest_value(std::uint32_t);
     void execute_alu_value(std::uint32_t);
     void execute_reg1_value(std::uint32_t);
     void execute_reg2_value(std::uint32_t);
     void execute_immediate_value(std::uint32_t);
+    void execute_regw_value(std::uint32_t);
+    void execute_memtoreg_value(std::uint32_t);
+    void execute_memwrite_value(std::uint32_t);
+    void execute_memread_value(std::uint32_t);
+    void execute_alusrc_value(std::uint32_t);
+    void execute_regdest_value(std::uint32_t);
     void memory_alu_value(std::uint32_t);
     void memory_rt_value(std::uint32_t);
     void memory_mem_value(std::uint32_t);
+    void memory_regw_value(std::uint32_t);
+    void memory_memtoreg_value(std::uint32_t);
+    void memory_memwrite_value(std::uint32_t);
+    void memory_memread_value(std::uint32_t);
     void writeback_value(std::uint32_t);
+    void writeback_regw_value(std::uint32_t);
 
 protected:
     virtual void do_step() = 0;