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* Define uncached region in range from 0xf0000000 to 0xffffffff.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
| | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Take into account actual requirements for rs, rt and rd write for individual ↵Pavel Pisa2019-02-04
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include more complex insert-sort test which checks memory and cache.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
| | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Simplify core test by use of common function to run test machine.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct write-back cache behavior.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include test for jump and link processing.Pavel Pisa2019-02-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add test for forwarding in ALU operations.Pavel Pisa2019-02-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct ALU test for SUB exception.Pavel Pisa2019-02-02
| | | | | | | | | | | | The operation 3 - 4 = 1 is legal integer arithmetic operation. Changed to 0x80000003 - 4 = 0x7fffffff 2147483651 - 4 = 2147483647 which overflows. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include support for JALR support.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct signed arithmetic overflow exception.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct processing of ORI, ANDI, XORI instructions which require ↵Pavel Pisa2019-01-31
| | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct hazards processing.Pavel Pisa2019-01-30
| | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Specify rpath during linking to find qtmips_machine library without install.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Hide some values that shouldn't been visible in no pipelined versionKarel Kočí2018-06-20
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* Fix value position for non-pipelined coreKarel Kočí2018-05-24
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* Add few more labelsKarel Kočí2018-05-24
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* Add few additional labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Add cache view rendererKarel Kočí2018-05-23
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* Ignore hazard unit for nowKarel Kočí2018-05-23
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* Add cache statisticsKarel Kočí2018-05-23
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* Fix load and store instructionsKarel Kočí2018-05-02
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* Initial implementation of cache viewKarel Kočí2018-04-17
| | | | It needs some more work to look nice but it already works.
* Drop unneeded parameter from CoreViewScene constructorKarel Kočí2018-04-17
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* Fix angle scroll speedKarel Kočí2018-04-17
| | | | | I finally manage to make device to report as angle scroll device. And it was too fast scroll so I make it solver. It is now some what acceptable.
* Store memory and program view address positionKarel Kočí2018-04-17
| | | | | | This reloads memoryview with same base address as it was closed with. It somewhat works but with program view it seems to be buggy and shifts stuff down. But let's say that it's good enough for now.
* When changing focus load it back to edit field in memoryviewKarel Kočí2018-04-15
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* Add 2x speedKarel Kočí2018-04-15
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* Disable memory protection configuration fields for nowKarel Kočí2018-04-15
| | | | | Memory protection is not feature that is strictly required. Because of that it's implementation has lower priority.
* Change presetsKarel Kočí2018-04-15
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* Rename CoreView to GraphicsViewKarel Kočí2018-04-15
| | | | | This generalizes CoreView to be used with other parts of the project too.
* Add cache dockKarel Kočí2018-04-15
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* Fix coverview memory cacheKarel Kočí2018-04-15
| | | | Text was always rendered.
* Show cache statistics in Memory block in coreviewKarel Kočí2018-04-15
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* Disable program followKarel Kočí2018-04-14
| | | | | | | | This should be easy enought to program but it requires some deeper changes to memoryview it self (to allows direct address to item mapping). Because of that I am disabling it for now and I will return to this feature in future. For now I am focusing on other more important aspects of qtmips (to make it feature complete not nice to use).
* Wire up missing control connectionsKarel Kočí2018-04-14
| | | | | Now only hazard unit is missing all wires. Anything else is wired up already.
* Drop quick jump buttons from memory viewKarel Kočí2018-04-10
| | | | | They are not implemented and even if they would they usage would be little bit funky as they would jump by internal amount of page memory.
* Fix some instruction string representationKarel Kočí2018-04-08
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