| Commit message (Collapse) | Author | Age |
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Remaining are MOVZ and MOVN in the execution phase
and all branch and jump operations in handle_pc().
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows to specify requirement for RS and RD on instruction
basis even for T_R / ALU instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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When any variant of cache instruction is detected
flush and invalidate whole data cache.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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instructions.
The previous code worked by chance only because decode has been fully
processed including forwarding from M and W before PC processing
started. But in real hardware the PC processing runs in parallel
with ALU and cannot read its results in the same cycle.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The operation 3 - 4 = 1 is legal integer arithmetic
operation. Changed to
0x80000003 - 4 = 0x7fffffff
2147483651 - 4 = 2147483647
which overflows.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The JR, BEQ, BNE are most probably incorrect still.
There is missing forwarding for pipelined execution.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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zero-extended immediate.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The shorter loop has priority. This is achieved by later
processing when it replaces possible result from longer
loop over W stage.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It needs some more work to look nice but it already works.
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I finally manage to make device to report as angle scroll device. And it
was too fast scroll so I make it solver. It is now some what acceptable.
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This reloads memoryview with same base address as it was closed with.
It somewhat works but with program view it seems to be buggy and shifts
stuff down. But let's say that it's good enough for now.
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Memory protection is not feature that is strictly required. Because of
that it's implementation has lower priority.
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This generalizes CoreView to be used with other parts of the project
too.
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Text was always rendered.
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This should be easy enought to program but it requires some deeper
changes to memoryview it self (to allows direct address to item
mapping). Because of that I am disabling it for now and I will return to
this feature in future. For now I am focusing on other more important
aspects of qtmips (to make it feature complete not nice to use).
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Now only hazard unit is missing all wires. Anything else is wired up
already.
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They are not implemented and even if they would they usage would be
little bit funky as they would jump by internal amount of page memory.
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