Distinguish between write-through cache with allocate and update only if hit.

Add into cache statistic number of backing/main memory accesses.
Correction of meaning and computation of the cache statistic.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

1 files changed, 4 insertions, 2 deletions

diff --git a/qtmips_machine/tests/tst_machine.h b/qtmips_machine/tests/tst_machine.h
index 0f9d753..938a9a8 100644
--- a/qtmips_machine/tests/tst_machine.h
+++ b/qtmips_machine/tests/tst_machine.h
@@ -91,11 +91,13 @@ private Q_SLOTS:
     void pipecorestall_alu_forward_data();
     void singlecore_memory_tests_data();
     void pipecore_nc_memory_tests_data();
-    void pipecore_wt_memory_tests_data();
+    void pipecore_wt_na_memory_tests_data();
+    void pipecore_wt_a_memory_tests_data();
     void pipecore_wb_memory_tests_data();
     void singlecore_memory_tests();
     void pipecore_nc_memory_tests();
-    void pipecore_wt_memory_tests();
+    void pipecore_wt_na_memory_tests();
+    void pipecore_wt_a_memory_tests();
     void pipecore_wb_memory_tests();
     // Cache
     void cache_data();