From adb9f147e358f687b37f5bf14c68f559c7c86a79 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Wed, 20 Feb 2019 14:17:32 +0100 Subject: Distinguish between write-through cache with allocate and update only if hit. Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa --- qtmips_machine/tests/tst_machine.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'qtmips_machine/tests/tst_machine.h') diff --git a/qtmips_machine/tests/tst_machine.h b/qtmips_machine/tests/tst_machine.h index 0f9d753..938a9a8 100644 --- a/qtmips_machine/tests/tst_machine.h +++ b/qtmips_machine/tests/tst_machine.h @@ -91,11 +91,13 @@ private Q_SLOTS: void pipecorestall_alu_forward_data(); void singlecore_memory_tests_data(); void pipecore_nc_memory_tests_data(); - void pipecore_wt_memory_tests_data(); + void pipecore_wt_na_memory_tests_data(); + void pipecore_wt_a_memory_tests_data(); void pipecore_wb_memory_tests_data(); void singlecore_memory_tests(); void pipecore_nc_memory_tests(); - void pipecore_wt_memory_tests(); + void pipecore_wt_na_memory_tests(); + void pipecore_wt_a_memory_tests(); void pipecore_wb_memory_tests(); // Cache void cache_data(); -- cgit v1.2.3