Distinguish between write-through cache with allocate and update only if hit.

Add into cache statistic number of backing/main memory accesses.
Correction of meaning and computation of the cache statistic.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

3 files changed, 31 insertions, 6 deletions

diff --git a/qtmips_machine/tests/testcache.cpp b/qtmips_machine/tests/testcache.cpp
index bbe1e62..92af45f 100644
--- a/qtmips_machine/tests/testcache.cpp
+++ b/qtmips_machine/tests/testcache.cpp
@@ -44,7 +44,7 @@ void MachineTests::cache_data() {
     QTest::addColumn<unsigned>("miss");
 
     MachineConfigCache cache_c;
-    cache_c.set_write_policy(MachineConfigCache::WP_TROUGH);
+    cache_c.set_write_policy(MachineConfigCache::WP_TROUGH_ALLOC);
     cache_c.set_enabled(true);
     cache_c.set_sets(8);
     cache_c.set_blocks(1);
diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp
index 65b529a..01307a5 100644
--- a/qtmips_machine/tests/testcore.cpp
+++ b/qtmips_machine/tests/testcore.cpp
@@ -835,7 +835,11 @@ void MachineTests::pipecore_nc_memory_tests_data() {
     core_memory_tests_data();
 }
 
-void MachineTests::pipecore_wt_memory_tests_data() {
+void MachineTests::pipecore_wt_na_memory_tests_data() {
+    core_memory_tests_data();
+}
+
+void MachineTests::pipecore_wt_a_memory_tests_data() {
     core_memory_tests_data();
 }
 
@@ -863,7 +867,26 @@ void MachineTests::pipecore_nc_memory_tests() {
     run_code_fragment(core, reg_init, reg_res, mem_init, mem_res, code);
 }
 
-void MachineTests::pipecore_wt_memory_tests() {
+void MachineTests::pipecore_wt_na_memory_tests() {
+    QFETCH(QVector<uint32_t>, code);
+    QFETCH(Registers, reg_init);
+    QFETCH(Registers, reg_res);
+    QFETCH(Memory, mem_init);
+    QFETCH(Memory, mem_res);
+    MachineConfigCache cache_conf;
+    cache_conf.set_enabled(true);
+    cache_conf.set_sets(2); // Number of sets
+    cache_conf.set_blocks(1); // Number of blocks
+    cache_conf.set_associativity(2); // Degree of associativity
+    cache_conf.set_replacement_policy(MachineConfigCache::RP_LRU);
+    cache_conf.set_write_policy(MachineConfigCache::WP_TROUGH_NOALLOC);
+    Cache i_cache(&mem_init, &cache_conf);
+    Cache d_cache(&mem_init, &cache_conf);
+    CorePipelined core(&reg_init, &i_cache, &d_cache, MachineConfig::HU_STALL_FORWARD);
+    run_code_fragment(core, reg_init, reg_res, mem_init, mem_res, code);
+}
+
+void MachineTests::pipecore_wt_a_memory_tests() {
     QFETCH(QVector<uint32_t>, code);
     QFETCH(Registers, reg_init);
     QFETCH(Registers, reg_res);
@@ -875,7 +898,7 @@ void MachineTests::pipecore_wt_memory_tests() {
     cache_conf.set_blocks(1); // Number of blocks
     cache_conf.set_associativity(2); // Degree of associativity
     cache_conf.set_replacement_policy(MachineConfigCache::RP_LRU);
-    cache_conf.set_write_policy(MachineConfigCache::WP_TROUGH);
+    cache_conf.set_write_policy(MachineConfigCache::WP_TROUGH_ALLOC);
     Cache i_cache(&mem_init, &cache_conf);
     Cache d_cache(&mem_init, &cache_conf);
     CorePipelined core(&reg_init, &i_cache, &d_cache, MachineConfig::HU_STALL_FORWARD);
diff --git a/qtmips_machine/tests/tst_machine.h b/qtmips_machine/tests/tst_machine.h
index 0f9d753..938a9a8 100644
--- a/qtmips_machine/tests/tst_machine.h
+++ b/qtmips_machine/tests/tst_machine.h
@@ -91,11 +91,13 @@ private Q_SLOTS:
     void pipecorestall_alu_forward_data();
     void singlecore_memory_tests_data();
     void pipecore_nc_memory_tests_data();
-    void pipecore_wt_memory_tests_data();
+    void pipecore_wt_na_memory_tests_data();
+    void pipecore_wt_a_memory_tests_data();
     void pipecore_wb_memory_tests_data();
     void singlecore_memory_tests();
     void pipecore_nc_memory_tests();
-    void pipecore_wt_memory_tests();
+    void pipecore_wt_na_memory_tests();
+    void pipecore_wt_a_memory_tests();
     void pipecore_wb_memory_tests();
     // Cache
     void cache_data();