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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2020-04-30 22:38:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-30 22:38:04 +0200 |
| commit | 4e18ac008b2fa958f16e30b44da097d242d22470 (patch) | |
| tree | 7854d11ad3c48b081f5a9154f050d6989e4d8122 | |
| parent | 850d1e6b430c463a54bb1348967750a1e0baef51 (diff) | |
| parent | 2984e85365529e24253b56edd395b09454c4f4ac (diff) | |
| download | qtmips-4e18ac008b2fa958f16e30b44da097d242d22470.tar.gz qtmips-4e18ac008b2fa958f16e30b44da097d242d22470.tar.bz2 qtmips-4e18ac008b2fa958f16e30b44da097d242d22470.zip | |
Merge pull request #7 from Kaisrlik/feature/interrupt_routine
Fix instructions how to use serial port/UART receive interrupt.
| -rw-r--r-- | README.md | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -252,6 +252,9 @@ Following coprocessor 0 registers are recognized | $15,1 | EBase | Exception vector base register | | $16,0 | Config | Configuration registers | +`mtc0` and `mfc0` are used to copy value from/to general puropose registers +to/from comprocessor 0 register. + Hardware/special registers implemented: | Number | Name | Description | @@ -269,7 +272,7 @@ is 0x80000180. The base can be changed (`EBase` register) and then PC is set to address EBase + 0x180. This is in accordance with MIPS release 1 and 2 manuals. -Enable bit 10 (interrupt mask) in the Status register. Ensure that bit +Enable bit 11 (interrupt mask) in the Status register. Ensure that bit 1 (`EXL`) is zero and bit 0 (`IE`) is set to one. Enable interrupt in the receiver status register (bit 1 of `SERP_RX_ST_REG`). |