diff options
| author | Jan Kaisrlík <jan.kaisrlik@avast.com> | 2020-04-30 22:21:34 +0200 |
|---|---|---|
| committer | Jan Kaisrlík <jan.kaisrlik@avast.com> | 2020-04-30 22:21:34 +0200 |
| commit | 2984e85365529e24253b56edd395b09454c4f4ac (patch) | |
| tree | 7854d11ad3c48b081f5a9154f050d6989e4d8122 | |
| parent | c63d19cb4b906c94afc807a53d7ec5d4881b1cfa (diff) | |
| download | qtmips-2984e85365529e24253b56edd395b09454c4f4ac.tar.gz qtmips-2984e85365529e24253b56edd395b09454c4f4ac.tar.bz2 qtmips-2984e85365529e24253b56edd395b09454c4f4ac.zip | |
README.md: fix reference to uart rx interrupt mask
uart rx insterrupt is mapped to bit 11 (8 + 3)
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -272,7 +272,7 @@ is 0x80000180. The base can be changed (`EBase` register) and then PC is set to address EBase + 0x180. This is in accordance with MIPS release 1 and 2 manuals. -Enable bit 10 (interrupt mask) in the Status register. Ensure that bit +Enable bit 11 (interrupt mask) in the Status register. Ensure that bit 1 (`EXL`) is zero and bit 0 (`IE`) is set to one. Enable interrupt in the receiver status register (bit 1 of `SERP_RX_ST_REG`). |