From c63d19cb4b906c94afc807a53d7ec5d4881b1cfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Kaisrl=C3=ADk?= Date: Thu, 30 Apr 2020 17:44:21 +0200 Subject: README: add documentation how to modify comprocessor 0 regs --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index b3ee5c2..00784eb 100644 --- a/README.md +++ b/README.md @@ -252,6 +252,9 @@ Following coprocessor 0 registers are recognized | $15,1 | EBase | Exception vector base register | | $16,0 | Config | Configuration registers | +`mtc0` and `mfc0` are used to copy value from/to general puropose registers +to/from comprocessor 0 register. + Hardware/special registers implemented: | Number | Name | Description | -- cgit v1.2.3 From 2984e85365529e24253b56edd395b09454c4f4ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Kaisrl=C3=ADk?= Date: Thu, 30 Apr 2020 22:21:34 +0200 Subject: README.md: fix reference to uart rx interrupt mask uart rx insterrupt is mapped to bit 11 (8 + 3) --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 00784eb..f579e20 100644 --- a/README.md +++ b/README.md @@ -272,7 +272,7 @@ is 0x80000180. The base can be changed (`EBase` register) and then PC is set to address EBase + 0x180. This is in accordance with MIPS release 1 and 2 manuals. -Enable bit 10 (interrupt mask) in the Status register. Ensure that bit +Enable bit 11 (interrupt mask) in the Status register. Ensure that bit 1 (`EXL`) is zero and bit 0 (`IE`) is set to one. Enable interrupt in the receiver status register (bit 1 of `SERP_RX_ST_REG`). -- cgit v1.2.3