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* Add write and read notification to the simple peripheral component.Pavel Pisa2019-02-08
* Exception handlers require even PC of the jump or branch instruction before d...Pavel Pisa2019-02-07
* Correct cache LocationStatus when cache is disabled.Pavel Pisa2019-02-07
* Implemented simple indication of presence of memory location in the cache.Pavel Pisa2019-02-07
* Added method to retrieve memory location status.Pavel Pisa2019-02-07
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Correct BLTZAL and BGEZAL execution to pass unmodified value to R31.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
* Provide at least partial cleanup after QtMipsMachine.Pavel Pisa2019-02-06
* Implement simple address-space ranges registration and example peripheral.Pavel Pisa2019-02-06
* Correct registers order in conversion to text for branch instructions.Pavel Pisa2019-02-06
* Include test for BGEZ, BGTZ, BLEZ, BLTZ, BEQ and BNE.Pavel Pisa2019-02-05
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen...Pavel Pisa2019-02-05
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
* Setup initial PC according executable entry form ELF file if it is non zero.Pavel Pisa2019-02-04
* Define uncached region in range from 0xf0000000 to 0xffffffff.Pavel Pisa2019-02-04
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Include more complex insert-sort test which checks memory and cache.Pavel Pisa2019-02-04
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
* Simplify core test by use of common function to run test machine.Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Correct write-back cache behavior.Pavel Pisa2019-02-04
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst...Pavel Pisa2019-02-02
* Include test for jump and link processing.Pavel Pisa2019-02-02
* Add test for forwarding in ALU operations.Pavel Pisa2019-02-02
* Correct ALU test for SUB exception.Pavel Pisa2019-02-02
* Include support for JALR support.Pavel Pisa2019-01-31
* Initial support for JAL.Pavel Pisa2019-01-31
* Correct signed arithmetic overflow exception.Pavel Pisa2019-01-31
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
* Correct processing of ORI, ANDI, XORI instructions which require zero-extende...Pavel Pisa2019-01-31
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
* Correct hazards processing.Pavel Pisa2019-01-30
* Add few more labelsKarel Kočí2018-05-24
* Add buses statis viewsKarel Kočí2018-05-24
* Add cache view rendererKarel Kočí2018-05-23
* Add cache statisticsKarel Kočí2018-05-23