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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-01-30 22:47:52 +0100 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-01-30 22:47:52 +0100 |
| commit | d33f4440e25dfef6aad971d483670ed21411492d (patch) | |
| tree | 06dc4605d7a1a2cdb452a8659c2a8ad49ea78911 /qtmips_machine | |
| parent | a7abf58e5eadbe3a5898d9a60f1e135aaa700c5d (diff) | |
| download | qtmips-d33f4440e25dfef6aad971d483670ed21411492d.tar.gz qtmips-d33f4440e25dfef6aad971d483670ed21411492d.tar.bz2 qtmips-d33f4440e25dfef6aad971d483670ed21411492d.zip | |
Do not replace rt by forward if instruction in T_R or store.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_machine')
| -rw-r--r-- | qtmips_machine/core.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index 17f2ccc..a2cc74b 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -377,7 +377,7 @@ void CorePipelined::do_step() { #define HAZARD(STAGE) ( \ (STAGE).regwrite && (STAGE).rwrite != 0 && \ ((STAGE).rwrite == dt_d.inst.rs() || ( \ - (dt_d.inst.type() == Instruction::T_R || (STAGE).inst.is_store()) && \ + (dt_d.inst.type() == Instruction::T_R || dt_d.inst.is_store()) && \ (STAGE).rwrite == dt_d.inst.rt()) \ )) // Note: We make exception with $0 as that has no effect and is used in nop instruction @@ -389,7 +389,8 @@ void CorePipelined::do_step() { dt_d.val_rs = dt_m.towrite_val; dt_d.ff_rs = FORWARD_FROM_M; } - if (dt_m.rwrite == dt_d.inst.rt()) { + if ((dt_d.inst.type() == Instruction::T_R || dt_d.inst.is_store()) && + (dt_m.rwrite == dt_d.inst.rt())) { dt_d.val_rt = dt_m.towrite_val; dt_d.ff_rt = FORWARD_FROM_M; } @@ -407,7 +408,8 @@ void CorePipelined::do_step() { dt_d.val_rs = dt_e.alu_val; dt_d.ff_rs = FORWARD_FROM_W; } - if (dt_e.rwrite == dt_d.inst.rt()) { + if ((dt_d.inst.type() == Instruction::T_R || dt_d.inst.is_store()) && + (dt_e.rwrite == dt_d.inst.rt())) { dt_d.val_rt = dt_e.alu_val; dt_d.ff_rt = FORWARD_FROM_W; } |