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* Include test for BGEZ, BGTZ, BLEZ, BLTZ, BEQ and BNE.Pavel Pisa2019-02-05
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen...Pavel Pisa2019-02-05
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
* Setup initial PC according executable entry form ELF file if it is non zero.Pavel Pisa2019-02-04
* Define uncached region in range from 0xf0000000 to 0xffffffff.Pavel Pisa2019-02-04
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Include more complex insert-sort test which checks memory and cache.Pavel Pisa2019-02-04
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
* Simplify core test by use of common function to run test machine.Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Correct write-back cache behavior.Pavel Pisa2019-02-04
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst...Pavel Pisa2019-02-02
* Include test for jump and link processing.Pavel Pisa2019-02-02
* Add test for forwarding in ALU operations.Pavel Pisa2019-02-02
* Correct ALU test for SUB exception.Pavel Pisa2019-02-02
* Include support for JALR support.Pavel Pisa2019-01-31
* Initial support for JAL.Pavel Pisa2019-01-31
* Correct signed arithmetic overflow exception.Pavel Pisa2019-01-31
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
* Correct processing of ORI, ANDI, XORI instructions which require zero-extende...Pavel Pisa2019-01-31
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
* Correct hazards processing.Pavel Pisa2019-01-30
* Add few more labelsKarel Kočí2018-05-24
* Add buses statis viewsKarel Kočí2018-05-24
* Add cache view rendererKarel Kočí2018-05-23
* Add cache statisticsKarel Kočí2018-05-23
* Fix load and store instructionsKarel Kočí2018-05-02
* Initial implementation of cache viewKarel Kočí2018-04-17
* Change presetsKarel Kočí2018-04-15
* Show cache statistics in Memory block in coreviewKarel Kočí2018-04-15
* Drop quick jump buttons from memory viewKarel Kočí2018-04-10
* Fix some instruction string representationKarel Kočí2018-04-08
* Change string format for some instructionKarel Kočí2018-04-08
* Implement LUIKarel Kočí2018-04-08
* Implement sync for memoryKarel Kočí2018-04-08
* Ensure that set, block and assoc. is in minimum oneKarel Kočí2018-04-08
* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
* Add associative cacheKarel Kočí2018-04-08
* Drop unneeded mask in memory implementationKarel Kočí2018-04-07
* Add initial implementatio of cachesKarel Kočí2018-04-07
* Just note that we are checking endianity automaticallyKarel Kočí2018-04-05
* Use whole words in memoryKarel Kočí2018-04-05