aboutsummaryrefslogtreecommitdiff
path: root/qtmips_machine
Commit message (Expand)AuthorAge
* qtmips_cli: add option to report number of required cycles and stalls.Pavel Pisa2019-04-05
* Implement stall cycles counter and view of CPU cycles counter.Pavel Pisa2019-04-02
* Coreview multiplexers updated and added for branch compare forward.Pavel Pisa2019-04-01
* Set gray background to stalled instructions/idled stages.Pavel Pisa2019-03-31
* Change single cycle core with delay slot to use separate fetch stage.Pavel Pisa2019-03-26
* Highlight instructions passing through the pipeline stages.Pavel Pisa2019-03-25
* Correct write through spelling. Reported by Richard Susta.Pavel Pisa2019-03-25
* Extend qtmips_cli to recognize break and report final state.Pavel Pisa2019-03-24
* Registers and cop0 state updates and reads are visualized by highlights.Pavel Pisa2019-03-17
* Highlight actual word read or written to the cache.Pavel Pisa2019-03-17
* Correct word in block visualization in cache view.Pavel Pisa2019-03-17
* Make use of QVERIFY_EXCEPTION_THROWN conditional, it is not available on Ubun...Pavel Pisa2019-03-15
* Switch to static libraries by default and ensure application rebuild when a l...Pavel Pisa2019-03-15
* Allow byte and half-word access to the peripherals.Pavel Pisa2019-03-13
* Fix LB and LH sign extension and LH/SH mask calculation.Pavel Pisa2019-03-13
* Correct use of uninitialized dt_d.num_rd and delete reported by valgrind.Pavel Pisa2019-03-12
* Fix program end by exception if divisor is zero for div instruction.Pavel Pisa2019-03-10
* Updated read and write, added open, close, ftruncate syscalls and fs_root opt...Pavel Pisa2019-03-09
* Correct exception setup - break and HW break should cause stop and step over.Pavel Pisa2019-03-06
* Enable configuration of syscalls emulation and stop on exception.Pavel Pisa2019-03-06
* Suppress warning where case fall-through is intentional.Pavel Pisa2019-03-06
* Correct parsing of register + offset operands, i.e., LW and SW.Pavel Pisa2019-03-06
* Try the strict check of encoded instructions and relax break and other.Pavel Pisa2019-03-05
* Complete revamp of disassembler and assembler arguments processing.Pavel Pisa2019-03-05
* Dock to view coprocessor 0 and cop0 counter/comparator support.Pavel Pisa2019-03-05
* Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM.Pavel Pisa2019-03-04
* Implemented interrupt delivery and processing for serial port.Pavel Pisa2019-03-04
* Implemented coprocessor 0 registers access and register EPC and Cause set by ...Pavel Pisa2019-03-04
* Simple serial port receive implementation.Pavel Pisa2019-02-25
* Exceptions causes align with SPIM and add serial port range alias equivalent ...Pavel Pisa2019-02-25
* Change serial port peripheral to match SPIM registers definition.Pavel Pisa2019-02-25
* Correct relative jumps range and adjust it for single core without delay-slot.Pavel Pisa2019-02-24
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
* Add some more labels and clarify rs, rt, rd in execute stage.Pavel Pisa2019-02-24
* Add support for goto to selected symbol address.Pavel Pisa2019-02-22
* Ensure that cache view and memory status are updated after cache flush.Pavel Pisa2019-02-21
* Added test for LWR, LWL, SWR and SWL instructions.Pavel Pisa2019-02-21
* Add burst time and store timing in the config.Pavel Pisa2019-02-21
* Distinguish between write-through cache with allocate and update only if hit.Pavel Pisa2019-02-20
* Update project files to adapt for release and debug libraries location for Wi...Pavel Pisa2019-02-19
* Clear LFU statistic for the kicked out cache-line.Pavel Pisa2019-02-18
* Report forward and stall for branches and add forward to execution phase.Pavel Pisa2019-02-18
* Correct ADD operation to map to ALU variant with overflow checking.Pavel Pisa2019-02-18
* Visualize request to stall and stall in execution phase and exception sources.Pavel Pisa2019-02-18
* Stall the pipeline even for branch which requires memory read as argument.Pavel Pisa2019-02-18
* Do not update instruction in the decode stage when stalled.Pavel Pisa2019-02-17
* Ignore LWC1, LWD1, SWC1 and SDC1 instructions.Pavel Pisa2019-02-17
* Pass arithmetic exception trough pipeline and implement trap support and inst...Pavel Pisa2019-02-17
* Change RGB LEDs signals and slots to unsigned value.Pavel Pisa2019-02-16
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15