Correct write through spelling. Reported by Richard Susta.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

5 files changed, 8 insertions, 8 deletions

diff --git a/qtmips_machine/cache.cpp b/qtmips_machine/cache.cpp
index ec6a021..b3afbeb 100644
--- a/qtmips_machine/cache.cpp
+++ b/qtmips_machine/cache.cpp
@@ -311,7 +311,7 @@ bool Cache::access(std::uint32_t address, std::uint32_t *data, bool write, std::
     // Need to find new block
     if (indx >= cnf.associativity()) {
         // if write through we do not need to alloecate cache line does not allocate
-        if (write && cnf.write_policy() == MachineConfigCache::WP_TROUGH_NOALLOC) {
+        if (write && cnf.write_policy() == MachineConfigCache::WP_THROUGH_NOALLOC) {
             miss_write++;
             emit miss_update(miss());
             update_statistics();
diff --git a/qtmips_machine/machineconfig.cpp b/qtmips_machine/machineconfig.cpp
index 272a7a6..c926348 100644
--- a/qtmips_machine/machineconfig.cpp
+++ b/qtmips_machine/machineconfig.cpp
@@ -55,7 +55,7 @@ using namespace machine;
 #define DFC_BLOCKS 1
 #define DFC_ASSOC 1
 #define DFC_REPLAC RP_RAND
-#define DFC_WRITE WP_TROUGH_NOALLOC
+#define DFC_WRITE WP_THROUGH_NOALLOC
 //////////////////////////////////////////////////////////////////////////////
 
 MachineConfigCache::MachineConfigCache() {
@@ -107,7 +107,7 @@ void MachineConfigCache::preset(enum ConfigPresets p) {
         set_blocks(2);
         set_associativity(2);
         set_replacement_policy(RP_RAND);
-        set_write_policy(WP_TROUGH_NOALLOC);
+        set_write_policy(WP_THROUGH_NOALLOC);
         break;
     case CP_SINGLE:
     case CP_PIPE_NO_HAZARD:
diff --git a/qtmips_machine/machineconfig.h b/qtmips_machine/machineconfig.h
index b8504b4..987f3aa 100644
--- a/qtmips_machine/machineconfig.h
+++ b/qtmips_machine/machineconfig.h
@@ -65,8 +65,8 @@ public:
     };
 
     enum WritePolicy {
-        WP_TROUGH_NOALLOC, // Write trough
-        WP_TROUGH_ALLOC, // Write trough
+        WP_THROUGH_NOALLOC, // Write through
+        WP_THROUGH_ALLOC, // Write through
         WP_BACK // Write back
     };
 
diff --git a/qtmips_machine/tests/testcache.cpp b/qtmips_machine/tests/testcache.cpp
index 92af45f..a760981 100644
--- a/qtmips_machine/tests/testcache.cpp
+++ b/qtmips_machine/tests/testcache.cpp
@@ -44,7 +44,7 @@ void MachineTests::cache_data() {
     QTest::addColumn<unsigned>("miss");
 
     MachineConfigCache cache_c;
-    cache_c.set_write_policy(MachineConfigCache::WP_TROUGH_ALLOC);
+    cache_c.set_write_policy(MachineConfigCache::WP_THROUGH_ALLOC);
     cache_c.set_enabled(true);
     cache_c.set_sets(8);
     cache_c.set_blocks(1);
diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp
index 53b6304..68da14c 100644
--- a/qtmips_machine/tests/testcore.cpp
+++ b/qtmips_machine/tests/testcore.cpp
@@ -981,7 +981,7 @@ void MachineTests::pipecore_wt_na_memory_tests() {
     cache_conf.set_blocks(1); // Number of blocks
     cache_conf.set_associativity(2); // Degree of associativity
     cache_conf.set_replacement_policy(MachineConfigCache::RP_LRU);
-    cache_conf.set_write_policy(MachineConfigCache::WP_TROUGH_NOALLOC);
+    cache_conf.set_write_policy(MachineConfigCache::WP_THROUGH_NOALLOC);
     Cache i_cache(&mem_init, &cache_conf);
     Cache d_cache(&mem_init, &cache_conf);
     CorePipelined core(&reg_init, &i_cache, &d_cache, MachineConfig::HU_STALL_FORWARD);
@@ -1000,7 +1000,7 @@ void MachineTests::pipecore_wt_a_memory_tests() {
     cache_conf.set_blocks(1); // Number of blocks
     cache_conf.set_associativity(2); // Degree of associativity
     cache_conf.set_replacement_policy(MachineConfigCache::RP_LRU);
-    cache_conf.set_write_policy(MachineConfigCache::WP_TROUGH_ALLOC);
+    cache_conf.set_write_policy(MachineConfigCache::WP_THROUGH_ALLOC);
     Cache i_cache(&mem_init, &cache_conf);
     Cache d_cache(&mem_init, &cache_conf);
     CorePipelined core(&reg_init, &i_cache, &d_cache, MachineConfig::HU_STALL_FORWARD);