| Commit message (Expand) | Author | Age |
|---|
| * | Implemented interrupt delivery and processing for serial port. | Pavel Pisa | 2019-03-04 |
| * | Implemented coprocessor 0 registers access and register EPC and Cause set by ... | Pavel Pisa | 2019-03-04 |
| * | Simple serial port receive implementation. | Pavel Pisa | 2019-02-25 |
| * | Exceptions causes align with SPIM and add serial port range alias equivalent ... | Pavel Pisa | 2019-02-25 |
| * | Change serial port peripheral to match SPIM registers definition. | Pavel Pisa | 2019-02-25 |
| * | Correct relative jumps range and adjust it for single core without delay-slot. | Pavel Pisa | 2019-02-24 |
| * | Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH. | Pavel Pisa | 2019-02-24 |
| * | Add some more labels and clarify rs, rt, rd in execute stage. | Pavel Pisa | 2019-02-24 |
| * | Add support for goto to selected symbol address. | Pavel Pisa | 2019-02-22 |
| * | Ensure that cache view and memory status are updated after cache flush. | Pavel Pisa | 2019-02-21 |
| * | Added test for LWR, LWL, SWR and SWL instructions. | Pavel Pisa | 2019-02-21 |
| * | Add burst time and store timing in the config. | Pavel Pisa | 2019-02-21 |
| * | Distinguish between write-through cache with allocate and update only if hit. | Pavel Pisa | 2019-02-20 |
| * | Update project files to adapt for release and debug libraries location for Wi... | Pavel Pisa | 2019-02-19 |
| * | Clear LFU statistic for the kicked out cache-line. | Pavel Pisa | 2019-02-18 |
| * | Report forward and stall for branches and add forward to execution phase. | Pavel Pisa | 2019-02-18 |
| * | Correct ADD operation to map to ALU variant with overflow checking. | Pavel Pisa | 2019-02-18 |
| * | Visualize request to stall and stall in execution phase and exception sources. | Pavel Pisa | 2019-02-18 |
| * | Stall the pipeline even for branch which requires memory read as argument. | Pavel Pisa | 2019-02-18 |
| * | Do not update instruction in the decode stage when stalled. | Pavel Pisa | 2019-02-17 |
| * | Ignore LWC1, LWD1, SWC1 and SDC1 instructions. | Pavel Pisa | 2019-02-17 |
| * | Pass arithmetic exception trough pipeline and implement trap support and inst... | Pavel Pisa | 2019-02-17 |
| * | Change RGB LEDs signals and slots to unsigned value. | Pavel Pisa | 2019-02-16 |
| * | Multiply and accumulate and CLZ/CLO operations added. | Pavel Pisa | 2019-02-15 |
| * | Implement EXT instruction used in GLIBC startup. | Pavel Pisa | 2019-02-15 |
| * | Core: move complex memory operation to own function and implement LWL, LWR, S... | Pavel Pisa | 2019-02-15 |
| * | Fill the rest of ALU opcode table to file all 64 entries. | Pavel Pisa | 2019-02-14 |
| * | Correct program loader to open ELF file in binary mode on Windows. | Pavel Pisa | 2019-02-14 |
| * | Ignore PREF instruction. | Pavel Pisa | 2019-02-14 |
| * | Implemented graphic representation and update of line and RGB LEDs. | Pavel Pisa | 2019-02-14 |
| * | Implement function to setup core C0 userlocal register. | Pavel Pisa | 2019-02-14 |
| * | Implement MUL operation which stores result to the register. | Pavel Pisa | 2019-02-14 |
| * | Ensure that single step does not run chunk of instructions instead of one. | Pavel Pisa | 2019-02-13 |
| * | Implemented three dials equivalent to MZ_APO RGB dials. | Pavel Pisa | 2019-02-13 |
| * | Initialize SP to safe RAM area. | Pavel Pisa | 2019-02-13 |
| * | Include simple serial port terminal and prepare empty peripheral dock. | Pavel Pisa | 2019-02-13 |
| * | Add speed option to run core for time chunks without visualization. | Pavel Pisa | 2019-02-13 |
| * | Add signals and multiplexers for ALU inputs forwarding. | Pavel Pisa | 2019-02-12 |
| * | Add ELF library even to the final executables linking to allow build with sta... | Pavel Pisa | 2019-02-12 |
| * | Make memory and program listing editable. | Pavel Pisa | 2019-02-12 |
| * | Implement LRU as simple priority queue with linear insert sort. | Pavel Pisa | 2019-02-12 |
| * | Add debug access to rword and friends to allow read data through cache withou... | Pavel Pisa | 2019-02-12 |
| * | Display red background for instruction causing exception and skip HW breakpoi... | Pavel Pisa | 2019-02-11 |
| * | Basic "hardware" breakpoints support implemented. | Pavel Pisa | 2019-02-11 |
| * | Prepare core for "hardware" breakpoints support and add signals to follow sta... | Pavel Pisa | 2019-02-11 |
| * | Correct build for LLVM. | Fanda Vacek | 2019-02-09 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Move computation of cache row, column and tag to single inline function. | Pavel Pisa | 2019-02-08 |
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ... | Pavel Pisa | 2019-02-08 |
