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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-08 19:11:45 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-08 19:11:45 +0100
commit5a4b106f98545c1593fa7104fc526c3bf6123698 (patch)
treec007eba82fe32e2fdda48070349aa7bdbf85731f /qtmips_machine
parentfb8fbbedea035fdf05987d1f6a32cb74de74d298 (diff)
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Accept SINC and SINCI instructions and flush even instruction cache on CACHE opcode.
Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_machine')
-rw-r--r--qtmips_machine/core.cpp8
-rw-r--r--qtmips_machine/instruction.cpp5
2 files changed, 9 insertions, 4 deletions
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 9312a69..75b6eb6 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -263,9 +263,10 @@ struct Core::dtMemory Core::memory(const struct dtExecute &dt) {
memwrite = false;
regwrite = false;
} else {
- if (dt.memctl == AC_CACHE_OP)
+ if (dt.memctl == AC_CACHE_OP) {
mem_data->sync();
- else if (memwrite) {
+ mem_program->sync();
+ } else if (memwrite) {
if (dt.memctl == AC_STORE_CONDITIONAL) {
mem_data->write_ctl(AC_WORD, mem_addr, dt.val_rt);
towrite_val = 1;
@@ -583,6 +584,9 @@ void CorePipelined::do_step() {
dt_e.regwrite, dt_e.inst.type(), dt_e.rwrite,
dt_m.regwrite, dt_m.inst.type(), dt_m.rwrite);
#endif
+#if 1
+ printf("PC 0x%08lx\n", (unsigned long)dt_f.inst_addr);
+#endif
// Now process program counter (loop connections from decode stage)
if (!stall) {
diff --git a/qtmips_machine/instruction.cpp b/qtmips_machine/instruction.cpp
index 694a32d..ad4ded3 100644
--- a/qtmips_machine/instruction.cpp
+++ b/qtmips_machine/instruction.cpp
@@ -111,7 +111,8 @@ static const struct InstructionMap alu_instruction_map[] = {
{"BREAK", IT_R, ALU_OP_BREAK, NOMEM, nullptr,
.flags = IMF_SUPPORTED | IMF_EXCEPTION},
IM_UNKNOWN,
- IM_UNKNOWN,
+ {"SYNC", IT_I, NOALU, NOMEM, nullptr, // SYNC
+ .flags = IMF_SUPPORTE},
{"MFHI", IT_R, ALU_OP_MFHI, NOMEM, nullptr,
.flags = FLAGS_ALU_T_R_D | IMF_READ_HILO},
{"MTHI", IT_R, ALU_OP_MTHI, NOMEM, nullptr,
@@ -276,7 +277,7 @@ static const struct InstructionMap regimm_instruction_map[] = {
IM_UNKNOWN,
IM_UNKNOWN,
{"SYNCI", IT_I, NOALU, NOMEM, nullptr, // SYNCI
- .flags = IMF_SUPPORTED | IMF_BJR_REQ_RS},
+ .flags = IMF_SUPPORTE},
};
const std::int32_t instruction_map_opcode_field = IMF_SUB_ENCODE(6, 26);