| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Ensure that single step does not run chunk of instructions instead of one. | Pavel Pisa | 2019-02-13 |
| * | Implemented three dials equivalent to MZ_APO RGB dials. | Pavel Pisa | 2019-02-13 |
| * | Initialize SP to safe RAM area. | Pavel Pisa | 2019-02-13 |
| * | Include simple serial port terminal and prepare empty peripheral dock. | Pavel Pisa | 2019-02-13 |
| * | Add speed option to run core for time chunks without visualization. | Pavel Pisa | 2019-02-13 |
| * | Add signals and multiplexers for ALU inputs forwarding. | Pavel Pisa | 2019-02-12 |
| * | Add ELF library even to the final executables linking to allow build with sta... | Pavel Pisa | 2019-02-12 |
| * | Make memory and program listing editable. | Pavel Pisa | 2019-02-12 |
| * | Implement LRU as simple priority queue with linear insert sort. | Pavel Pisa | 2019-02-12 |
| * | Add debug access to rword and friends to allow read data through cache withou... | Pavel Pisa | 2019-02-12 |
| * | Display red background for instruction causing exception and skip HW breakpoi... | Pavel Pisa | 2019-02-11 |
| * | Basic "hardware" breakpoints support implemented. | Pavel Pisa | 2019-02-11 |
| * | Prepare core for "hardware" breakpoints support and add signals to follow sta... | Pavel Pisa | 2019-02-11 |
| * | Correct build for LLVM. | Fanda Vacek | 2019-02-09 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Move computation of cache row, column and tag to single inline function. | Pavel Pisa | 2019-02-08 |
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ... | Pavel Pisa | 2019-02-08 |
| * | Document InstructionFlags meaning and remove unused IMF_MEM_STORE. | Pavel Pisa | 2019-02-08 |
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG... | Pavel Pisa | 2019-02-08 |
| * | Make function to register exception handler accessible from outside. | Pavel Pisa | 2019-02-08 |
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| * | Add write and read notification to the simple peripheral component. | Pavel Pisa | 2019-02-08 |
| * | Exception handlers require even PC of the jump or branch instruction before d... | Pavel Pisa | 2019-02-07 |
| * | Correct cache LocationStatus when cache is disabled. | Pavel Pisa | 2019-02-07 |
| * | Implemented simple indication of presence of memory location in the cache. | Pavel Pisa | 2019-02-07 |
| * | Added method to retrieve memory location status. | Pavel Pisa | 2019-02-07 |
| * | Correct display of jump and branch instructions. | Pavel Pisa | 2019-02-07 |
| * | Add address to emitted instruction to allow its use for branch address decoding. | Pavel Pisa | 2019-02-07 |
| * | Implemented basic infrastructure to handle exceptions. | Pavel Pisa | 2019-02-07 |
| * | Implement BSHFL instruction and ignore RDHWR instruction. | Pavel Pisa | 2019-02-07 |
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| * | Correct BLTZAL and BGEZAL execution to pass unmodified value to R31. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Resolve some memory leaks found by Valgrind. | Pavel Pisa | 2019-02-06 |
| * | Provide at least partial cleanup after QtMipsMachine. | Pavel Pisa | 2019-02-06 |
| * | Implement simple address-space ranges registration and example peripheral. | Pavel Pisa | 2019-02-06 |
| * | Correct registers order in conversion to text for branch instructions. | Pavel Pisa | 2019-02-06 |
| * | Include test for BGEZ, BGTZ, BLEZ, BLTZ, BEQ and BNE. | Pavel Pisa | 2019-02-05 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen... | Pavel Pisa | 2019-02-05 |
| * | Make instruction to text conversion more generic. | Pavel Pisa | 2019-02-05 |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Setup initial PC according executable entry form ELF file if it is non zero. | Pavel Pisa | 2019-02-04 |
| * | Define uncached region in range from 0xf0000000 to 0xffffffff. | Pavel Pisa | 2019-02-04 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Include more complex insert-sort test which checks memory and cache. | Pavel Pisa | 2019-02-04 |
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
