| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Implement MUL operation which stores result to the register. | Pavel Pisa | 2019-02-14 |
| * | Prepare core for "hardware" breakpoints support and add signals to follow sta... | Pavel Pisa | 2019-02-11 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| * | Added method to retrieve memory location status. | Pavel Pisa | 2019-02-07 |
| * | Implement BSHFL instruction and ignore RDHWR instruction. | Pavel Pisa | 2019-02-07 |
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
 |
index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
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