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path: root/qtmips_machine/machinedefs.h
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* Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM.Pavel Pisa2019-03-04
* Implemented coprocessor 0 registers access and register EPC and Cause set by ...Pavel Pisa2019-03-04
* Exceptions causes align with SPIM and add serial port range alias equivalent ...Pavel Pisa2019-02-25
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
* Pass arithmetic exception trough pipeline and implement trap support and inst...Pavel Pisa2019-02-17
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
* Core: move complex memory operation to own function and implement LWL, LWR, S...Pavel Pisa2019-02-15
* Implement MUL operation which stores result to the register.Pavel Pisa2019-02-14
* Prepare core for "hardware" breakpoints support and add signals to follow sta...Pavel Pisa2019-02-11
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
* Added method to retrieve memory location status.Pavel Pisa2019-02-07
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
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