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path: root/qtmips_machine/instruction.cpp
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* Suppress warning where case fall-through is intentional.Pavel Pisa2019-03-06
* Correct parsing of register + offset operands, i.e., LW and SW.Pavel Pisa2019-03-06
* Try the strict check of encoded instructions and relax break and other.Pavel Pisa2019-03-05
* Complete revamp of disassembler and assembler arguments processing.Pavel Pisa2019-03-05
* Implemented coprocessor 0 registers access and register EPC and Cause set by ...Pavel Pisa2019-03-04
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
* Correct ADD operation to map to ALU variant with overflow checking.Pavel Pisa2019-02-18
* Ignore LWC1, LWD1, SWC1 and SDC1 instructions.Pavel Pisa2019-02-17
* Pass arithmetic exception trough pipeline and implement trap support and inst...Pavel Pisa2019-02-17
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
* Core: move complex memory operation to own function and implement LWL, LWR, S...Pavel Pisa2019-02-15
* Fill the rest of ALU opcode table to file all 64 entries.Pavel Pisa2019-02-14
* Ignore PREF instruction.Pavel Pisa2019-02-14
* Implement MUL operation which stores result to the register.Pavel Pisa2019-02-14
* Make memory and program listing editable.Pavel Pisa2019-02-12
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ...Pavel Pisa2019-02-08
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG...Pavel Pisa2019-02-08
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Correct BLTZAL and BGEZAL execution to pass unmodified value to R31.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Correct registers order in conversion to text for branch instructions.Pavel Pisa2019-02-06
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen...Pavel Pisa2019-02-05
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
* Fix some instruction string representationKarel Kočí2018-04-08
* Change string format for some instructionKarel Kočí2018-04-08
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
* Another swap in instruction decodingKarel Kočí2018-02-14
* Swap rs and rt in I instructons decodingKarel Kočí2018-02-14
* Various graphics tweaksKarel Kočí2018-01-27
* Print I instruction immediate field in hexaKarel Kočí2018-01-17
* Reverse translate NOP correctlyKarel Kočí2018-01-15
* Allow instruction trace from any stageKarel Kočí2018-01-11
* Initial implementation of reverse instruction conversionKarel Kočí2018-01-03
* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17