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path: root/qtmips_machine/instruction.cpp
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* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ...Pavel Pisa2019-02-08
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG...Pavel Pisa2019-02-08
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Correct BLTZAL and BGEZAL execution to pass unmodified value to R31.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Correct registers order in conversion to text for branch instructions.Pavel Pisa2019-02-06
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen...Pavel Pisa2019-02-05
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
* Take into account actual requirements for rs, rt and rd write for individual ...Pavel Pisa2019-02-04
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
* Add license to the source files.Pavel Pisa2019-02-04
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
* Fix some instruction string representationKarel Kočí2018-04-08
* Change string format for some instructionKarel Kočí2018-04-08
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
* Another swap in instruction decodingKarel Kočí2018-02-14
* Swap rs and rt in I instructons decodingKarel Kočí2018-02-14
* Various graphics tweaksKarel Kočí2018-01-27
* Print I instruction immediate field in hexaKarel Kočí2018-01-17
* Reverse translate NOP correctlyKarel Kočí2018-01-15
* Allow instruction trace from any stageKarel Kočí2018-01-11
* Initial implementation of reverse instruction conversionKarel Kočí2018-01-03
* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
* Revert "Suppress some warning"Karel Kočí2017-12-17
* Suppress some warningKarel Kočí2017-12-12
* Test pipelined coreKarel Kočí2017-11-25
* Implement tests for few more arithmetic instructionsKarel Kočí2017-11-21
* Add possibility to compare memory and registers stateKarel Kočí2017-11-21
* Another huge pile of work for about two monthsKarel Kočí2017-11-19
* Add some more instructions to be decoded and arithmetic I testKarel Kočí2017-09-05
* Use QString and QVector instead of std ones and moreKarel Kočí2017-09-02
* Some to_string_hex cleanupsKarel Kočí2017-08-30
* Initial commitKarel Kočí2017-08-30