| Commit message (Expand) | Author | Age |
|---|
| * | Remove forgotten debug print in relocation code. | Pavel Pisa | 2019-07-18 |
| * | Simple assembler moved to separate class which is independent on Qt GUI API. | Pavel Pisa | 2019-07-17 |
| * | Instructions update and encoding enhanced. | Pavel Pisa | 2019-07-03 |
| * | Use explicitly declared empty stringlist for instructions without arguments. | Pavel Pisa | 2019-07-03 |
| * | Allow underscore in labels. | Pavel Pisa | 2019-07-03 |
| * | Add option to parse and show symbolic registers names. | Pavel Pisa | 2019-07-03 |
| * | Allow spaces in middle of assembler arguments and report errors. | Pavel Pisa | 2019-07-03 |
| * | Extend instruction parsing to accept numeric value continuing by expression. | Pavel Pisa | 2019-07-02 |
| * | Add binary complement operation to the parser. | Pavel Pisa | 2019-07-02 |
| * | Simple highlighter for assembly language added. | Pavel Pisa | 2019-07-02 |
| * | Teach simple embedded assembler .orig and .word directives. | Pavel Pisa | 2019-07-02 |
| * | Change instruction parsing to allow multiple words pseudo-operations. | Pavel Pisa | 2019-07-02 |
| * | Evaluation of symbolic expressions in assembler added. | Pavel Pisa | 2019-07-02 |
| * | Minimal prototype of integrated assembler. | Pavel Pisa | 2019-07-01 |
| * | Convert QString to C string character by character, std::strtol{l} fails unde... | Pavel Pisa | 2019-06-26 |
| * | Suppress warning where case fall-through is intentional. | Pavel Pisa | 2019-03-06 |
| * | Correct parsing of register + offset operands, i.e., LW and SW. | Pavel Pisa | 2019-03-06 |
| * | Try the strict check of encoded instructions and relax break and other. | Pavel Pisa | 2019-03-05 |
| * | Complete revamp of disassembler and assembler arguments processing. | Pavel Pisa | 2019-03-05 |
| * | Implemented coprocessor 0 registers access and register EPC and Cause set by ... | Pavel Pisa | 2019-03-04 |
| * | Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH. | Pavel Pisa | 2019-02-24 |
| * | Correct ADD operation to map to ALU variant with overflow checking. | Pavel Pisa | 2019-02-18 |
| * | Ignore LWC1, LWD1, SWC1 and SDC1 instructions. | Pavel Pisa | 2019-02-17 |
| * | Pass arithmetic exception trough pipeline and implement trap support and inst... | Pavel Pisa | 2019-02-17 |
| * | Multiply and accumulate and CLZ/CLO operations added. | Pavel Pisa | 2019-02-15 |
| * | Implement EXT instruction used in GLIBC startup. | Pavel Pisa | 2019-02-15 |
| * | Core: move complex memory operation to own function and implement LWL, LWR, S... | Pavel Pisa | 2019-02-15 |
| * | Fill the rest of ALU opcode table to file all 64 entries. | Pavel Pisa | 2019-02-14 |
| * | Ignore PREF instruction. | Pavel Pisa | 2019-02-14 |
| * | Implement MUL operation which stores result to the register. | Pavel Pisa | 2019-02-14 |
| * | Make memory and program listing editable. | Pavel Pisa | 2019-02-12 |
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ... | Pavel Pisa | 2019-02-08 |
| * | Document InstructionFlags meaning and remove unused IMF_MEM_STORE. | Pavel Pisa | 2019-02-08 |
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG... | Pavel Pisa | 2019-02-08 |
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| * | Correct display of jump and branch instructions. | Pavel Pisa | 2019-02-07 |
| * | Implement BSHFL instruction and ignore RDHWR instruction. | Pavel Pisa | 2019-02-07 |
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| * | Correct BLTZAL and BGEZAL execution to pass unmodified value to R31. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Correct registers order in conversion to text for branch instructions. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen... | Pavel Pisa | 2019-02-05 |
| * | Make instruction to text conversion more generic. | Pavel Pisa | 2019-02-05 |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
