| Commit message (Expand) | Author | Age |
|---|
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ... | Pavel Pisa | 2019-02-08 |
| * | Document InstructionFlags meaning and remove unused IMF_MEM_STORE. | Pavel Pisa | 2019-02-08 |
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG... | Pavel Pisa | 2019-02-08 |
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| * | Correct display of jump and branch instructions. | Pavel Pisa | 2019-02-07 |
| * | Implement BSHFL instruction and ignore RDHWR instruction. | Pavel Pisa | 2019-02-07 |
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| * | Correct BLTZAL and BGEZAL execution to pass unmodified value to R31. | Pavel Pisa | 2019-02-07 |
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| * | Correct registers order in conversion to text for branch instructions. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen... | Pavel Pisa | 2019-02-05 |
| * | Make instruction to text conversion more generic. | Pavel Pisa | 2019-02-05 |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| * | Fix some instruction string representation | Karel Kočí | 2018-04-08 |
| * | Change string format for some instruction | Karel Kočí | 2018-04-08 |
| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 |
| * | Another swap in instruction decoding | Karel Kočí | 2018-02-14 |
| * | Swap rs and rt in I instructons decoding | Karel Kočí | 2018-02-14 |
| * | Various graphics tweaks | Karel Kočí | 2018-01-27 |
| * | Print I instruction immediate field in hexa | Karel Kočí | 2018-01-17 |
| * | Reverse translate NOP correctly | Karel Kočí | 2018-01-15 |
| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| * | Initial implementation of reverse instruction conversion | Karel Kočí | 2018-01-03 |
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
| * | Revert "Suppress some warning" | Karel Kočí | 2017-12-17 |
| * | Suppress some warning | Karel Kočí | 2017-12-12 |
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
| * | Implement tests for few more arithmetic instructions | Karel Kočí | 2017-11-21 |
| * | Add possibility to compare memory and registers state | Karel Kočí | 2017-11-21 |
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| * | Add some more instructions to be decoded and arithmetic I test | Karel Kočí | 2017-09-05 |
| * | Use QString and QVector instead of std ones and more | Karel Kočí | 2017-09-02 |
| * | Some to_string_hex cleanups | Karel Kočí | 2017-08-30 |
| * | Initial commit | Karel Kočí | 2017-08-30 |
