| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| | | | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Take into account actual requirements for rs, rt and rd write for individual ↵ | Pavel Pisa | 2019-02-04 |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| | | | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵ | Pavel Pisa | 2019-02-02 |
| | | | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| | | | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct processing of ORI, ANDI, XORI instructions which require ↵ | Pavel Pisa | 2019-01-31 |
| | | | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add few more labels | Karel Kočí | 2018-05-24 |
| | | |||
| * | Add buses statis views | Karel Kočí | 2018-05-24 |
| | | |||
| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
| | | |||
| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
| | | |||
| * | Add instruction view to single core | Karel Kočí | 2018-01-21 |
| | | |||
| * | Implement hazard unit | Karel Kočí | 2018-01-15 |
| | | |||
| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| | | | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user. | ||
| * | Implement machine restart | Karel Kočí | 2018-01-05 |
| | | |||
| * | Allow delay slot disable for non-pipelined core | Karel Kočí | 2018-01-03 |
| | | |||
| * | Add trace-feth to qtmips_cli | Karel Kočí | 2018-01-03 |
| | | |||
| * | Use global includes in qtmips_machine | Karel Kočí | 2017-12-17 |
| | | |||
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
| | | |||
| * | Implement some store and load instructions | Karel Kočí | 2017-12-12 |
| | | |||
| * | Tiny cleanup | Karel Kočí | 2017-12-12 |
| | | |||
| * | Implement branch and jump instructions | Karel Kočí | 2017-12-12 |
| | | |||
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
| | | |||
| * | Implement some immediate arithmetic instructions | Karel Kočí | 2017-11-21 |
| | | |||
| * | Implement and test ADD | Karel Kočí | 2017-11-21 |
| | | |||
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| | | | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression. | ||
| * | Initial commit | Karel Kočí | 2017-08-30 |
| Adding work done so far. | |||
 |
index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
| aboutsummaryrefslogtreecommitdiff |