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* Prepare core for "hardware" breakpoints support and add signals to follow ↵Pavel Pisa2019-02-11
| | | | | | stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Exception handlers require even PC of the jump or branch instruction before ↵Pavel Pisa2019-02-07
| | | | | | | | | | | delay slot. When exception occurs at instruction in delay slot, the address of branch/delay instruction is stored to EPC instead of address of instruction causing the exception. So that address has to be delivered to exception handling object. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
| | | | | | | | The new Qt5 syntax is used to create connections because old syntax does not work with multiple arguments for some unresolved reason. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented base for exception handling.Pavel Pisa2019-02-06
| | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Take into account actual requirements for rs, rt and rd write for individual ↵Pavel Pisa2019-02-04
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct processing of ORI, ANDI, XORI instructions which require ↵Pavel Pisa2019-01-31
| | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add few more labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Implement sync for memoryKarel Kočí2018-04-08
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* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
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* Add instruction view to single coreKarel Kočí2018-01-21
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* Implement hazard unitKarel Kočí2018-01-15
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* Allow instruction trace from any stageKarel Kočí2018-01-11
| | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user.
* Implement machine restartKarel Kočí2018-01-05
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* Allow delay slot disable for non-pipelined coreKarel Kočí2018-01-03
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* Add trace-feth to qtmips_cliKarel Kočí2018-01-03
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* Use global includes in qtmips_machineKarel Kočí2017-12-17
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* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
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* Implement some store and load instructionsKarel Kočí2017-12-12
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* Tiny cleanupKarel Kočí2017-12-12
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* Implement branch and jump instructionsKarel Kočí2017-12-12
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* Test pipelined coreKarel Kočí2017-11-25
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* Implement some immediate arithmetic instructionsKarel Kočí2017-11-21
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* Implement and test ADDKarel Kočí2017-11-21
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* Another huge pile of work for about two monthsKarel Kočí2017-11-19
| | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression.
* Initial commitKarel Kočí2017-08-30
Adding work done so far.
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