diff options
Diffstat (limited to 'qtmips_machine/tests')
| -rw-r--r-- | qtmips_machine/tests/testalu.cpp | 67 | ||||
| -rw-r--r-- | qtmips_machine/tests/testcore.cpp | 35 |
2 files changed, 95 insertions, 7 deletions
diff --git a/qtmips_machine/tests/testalu.cpp b/qtmips_machine/tests/testalu.cpp index aad101f..b45a317 100644 --- a/qtmips_machine/tests/testalu.cpp +++ b/qtmips_machine/tests/testalu.cpp @@ -7,58 +7,117 @@ void MachineTests::alu_data() { QTest::addColumn<std::uint32_t>("s"); QTest::addColumn<std::uint32_t>("t"); QTest::addColumn<std::uint8_t>("sa"); + QTest::addColumn<Registers>("regs_init"); + QTest::addColumn<Registers>("regs_res"); QTest::addColumn<std::uint32_t>("res"); // TODO SLL-SRAV + { + Registers init; + init.write_hi_lo(true, 42); + init.write_hi_lo(false, 24); + Registers res(init); + QTest::newRow("MFHI") << ALU_OP_MFHI \ + << (std::uint32_t)0 \ + << (std::uint32_t)0 \ + << (std::uint8_t)0 \ + << init \ + << res \ + << (std::uint32_t)42; + QTest::newRow("MFLO") << ALU_OP_MFLO \ + << (std::uint32_t)0 \ + << (std::uint32_t)0 \ + << (std::uint8_t)0 \ + << init \ + << res \ + << (std::uint32_t)24; + res.write_hi_lo(true, 43); + QTest::newRow("MTHI") << ALU_OP_MTHI \ + << (std::uint32_t)43 \ + << (std::uint32_t)0 \ + << (std::uint8_t)0 \ + << init \ + << res \ + << (std::uint32_t)0; + res.write_hi_lo(true, 42); + res.write_hi_lo(false, 23); + QTest::newRow("MTLO") << ALU_OP_MTLO \ + << (std::uint32_t)23 \ + << (std::uint32_t)0 \ + << (std::uint8_t)0 \ + << init \ + << res \ + << (std::uint32_t)0; + } QTest::newRow("ADD") << ALU_OP_ADD \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)90; QTest::newRow("ADDU") << ALU_OP_ADDU \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)90; QTest::newRow("SUB") << ALU_OP_SUB \ << (std::uint32_t)66 \ << (std::uint32_t)24 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)42; QTest::newRow("SUBU") << ALU_OP_SUBU \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)-42; QTest::newRow("AND") << ALU_OP_AND \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)0x201; QTest::newRow("OR") << ALU_OP_OR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)0xE83; QTest::newRow("XOR") << ALU_OP_XOR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)0xC82; QTest::newRow("NOR") << ALU_OP_NOR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)0xFFFFF17C; QTest::newRow("SLT") << ALU_OP_SLT \ << (std::uint32_t)-31 \ << (std::uint32_t)24 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)1; QTest::newRow("SLTU") << ALU_OP_SLTU \ << (std::uint32_t)24 \ << (std::uint32_t)32 \ << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ << (std::uint32_t)1; } @@ -67,9 +126,12 @@ void MachineTests::alu() { QFETCH(std::uint32_t, s); QFETCH(std::uint32_t, t); QFETCH(std::uint8_t, sa); + QFETCH(Registers, regs_init); + QFETCH(Registers, regs_res); QFETCH(std::uint32_t, res); - QCOMPARE(alu_operate(op, s , t, sa), res); + QCOMPARE(alu_operate(op, s , t, sa, ®s_init), res); + QCOMPARE(regs_res, regs_init); } void MachineTests::alu_except_data() { @@ -94,7 +156,8 @@ void MachineTests::alu_except() { QFETCH(std::uint8_t, op); QFETCH(std::uint32_t, s); QFETCH(std::uint32_t, t); + Registers regs; // Only runtime exception is expected as any other exception is a bug - QVERIFY_EXCEPTION_THROWN(alu_operate((enum AluOp)op, s , t, 0), QtMipsExceptionRuntime); + QVERIFY_EXCEPTION_THROWN(alu_operate((enum AluOp)op, s , t, 0, ®s), QtMipsExceptionRuntime); } diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index 31f61ab..835dd2c 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -121,6 +121,34 @@ static void core_regs_data() { << regs_init \ << regs_res; } + + // Move instructions + { + Registers regs_init; + regs_init.write_hi_lo(true, 24); + regs_init.write_hi_lo(false, 28); + regs_init.write_gp(27, 21); + regs_init.write_gp(28, 22); + Registers regs_res(regs_init); + regs_res.write_gp(26, 24); + QTest::newRow("MFHI") << Instruction(0, 0, 0, 26, 0, 16) \ + << regs_init \ + << regs_res; + regs_res.write_gp(26, 28); + QTest::newRow("MFLO") << Instruction(0, 0, 0, 26, 0, 18) \ + << regs_init \ + << regs_res; + regs_res.write_gp(26, 0); + regs_res.write_hi_lo(true, 21); + QTest::newRow("MTHI") << Instruction(0, 27, 0, 0, 0, 17) \ + << regs_init \ + << regs_res; + regs_res.write_hi_lo(true, 24); + regs_res.write_hi_lo(false, 22); + QTest::newRow("MTLO") << Instruction(0, 28, 0, 0, 0, 19) \ + << regs_init \ + << regs_res; + } } void MachineTests::singlecore_regs_data() { @@ -160,20 +188,17 @@ void MachineTests::pipecore_regs() { mem.write_word(res.read_pc(), i.data()); // Store single instruction (anything else should be 0 so NOP effectively) Memory mem_used(mem); - Registers regs_used(init); res.pc_jmp(0x14); - CorePipelined core(®s_used, &mem_used); + CorePipelined core(&init, &mem_used); for (int i = 0; i < 4; i++) { core.step(); // Fire steps for five pipelines stages - init.pc_inc(); - QCOMPARE(init, regs_used); // Untill writeback there should be no change in registers } core.step(); //cout << "well:" << init.read_gp(26) << ":" << regs_used.read_gp(26) << endl; - QCOMPARE(regs_used, res); // After doing changes from initial state this should be same state as in case of passed expected result + QCOMPARE(init, res); // After doing changes from initial state this should be same state as in case of passed expected result QCOMPARE(mem, mem_used); // There should be no change in memory } |