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| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -20,7 +20,7 @@ The used [MIPS CPU](https://en.wikipedia.org/wiki/MIPS_architecture) building bl and a pipeline model matches lecture slides prepared by Michal Štepanovský for the subject [Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start). The course is based on the book [Computer Organization and Design, The HW/SW Interface](https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3) written by -professors Paterson and Henessy. +professors Patterson and Henessy. Additional documentation can be found in subdirectory [`docs`](docs) of the project. |