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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-10-15 11:04:46 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-10-16 05:51:57 +0200 |
| commit | a88666263efba6712823960e9a32d1b3ab381472 (patch) | |
| tree | 7f5e49c57d04ac69c85003259c5dd97da5028b8c | |
| parent | 9aa03382ea46f87f336dd8f55bcd17423d1632b5 (diff) | |
| download | qtmips-a88666263efba6712823960e9a32d1b3ab381472.tar.gz qtmips-a88666263efba6712823960e9a32d1b3ab381472.tar.bz2 qtmips-a88666263efba6712823960e9a32d1b3ab381472.zip | |
README: correct typo in professor Patterson name.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -20,7 +20,7 @@ The used [MIPS CPU](https://en.wikipedia.org/wiki/MIPS_architecture) building bl and a pipeline model matches lecture slides prepared by Michal Štepanovský for the subject [Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start). The course is based on the book [Computer Organization and Design, The HW/SW Interface](https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3) written by -professors Paterson and Henessy. +professors Patterson and Henessy. Additional documentation can be found in subdirectory [`docs`](docs) of the project. |