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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-02-04 13:19:10 +0100 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-02-04 13:19:10 +0100 |
| commit | 11e55482f80e5bf7df19f845c2d4faf5a9a6010c (patch) | |
| tree | ed6e21378212c2386c976367200584ea8c46f8e2 /tests/cpu_trap/trap.S | |
| parent | fed3a4f559984ec77961f6d5556e183db6f41a2d (diff) | |
| download | qtmips-11e55482f80e5bf7df19f845c2d4faf5a9a6010c.tar.gz qtmips-11e55482f80e5bf7df19f845c2d4faf5a9a6010c.tar.bz2 qtmips-11e55482f80e5bf7df19f845c2d4faf5a9a6010c.zip | |
Primitive implementation of cache instruction.
When any variant of cache instruction is detected
flush and invalidate whole data cache.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'tests/cpu_trap/trap.S')
0 files changed, 0 insertions, 0 deletions