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| author | Karel Kočí <cynerd@email.cz> | 2018-01-15 14:36:31 +0100 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2018-01-15 14:36:31 +0100 |
| commit | ed851a24951417b2493211835f9e488448890be6 (patch) | |
| tree | e9e3647ab470c10da519ec4593834979d17f7852 /qtmips_machine/tests | |
| parent | 78534f29b90fcf7484ed8b64e404a7059a69abea (diff) | |
| download | qtmips-ed851a24951417b2493211835f9e488448890be6.tar.gz qtmips-ed851a24951417b2493211835f9e488448890be6.tar.bz2 qtmips-ed851a24951417b2493211835f9e488448890be6.zip | |
Fix SRA and SRAV instructions
This implementation is correct one but there is no guarantee that it
will work with all compilers so we should always check on given platform
that tests pass (and potentially fix it).
Diffstat (limited to 'qtmips_machine/tests')
| -rw-r--r-- | qtmips_machine/tests/testalu.cpp | 44 | ||||
| -rw-r--r-- | qtmips_machine/tests/testcore.cpp | 2 |
2 files changed, 44 insertions, 2 deletions
diff --git a/qtmips_machine/tests/testalu.cpp b/qtmips_machine/tests/testalu.cpp index 7668679..a701b64 100644 --- a/qtmips_machine/tests/testalu.cpp +++ b/qtmips_machine/tests/testalu.cpp @@ -13,7 +13,49 @@ void MachineTests::alu_data() { QTest::addColumn<Registers>("regs_res"); QTest::addColumn<std::uint32_t>("res"); - // TODO SLL-SRAV + QTest::newRow("SLL") << ALU_OP_SLL \ + << (std::uint32_t)0 \ + << (std::uint32_t)0x80000001 \ + << (std::uint8_t)3 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0x8; + QTest::newRow("SRL") << ALU_OP_SRL \ + << (std::uint32_t)0 \ + << (std::uint32_t)0x80000008 \ + << (std::uint8_t)3 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0x10000001; + QTest::newRow("SRA") << ALU_OP_SRA \ + << (std::uint32_t)0 \ + << (std::uint32_t)0x80000008 \ + << (std::uint8_t)3 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0xF0000001; + QTest::newRow("SLLV") << ALU_OP_SLLV \ + << (std::uint32_t)3 \ + << (std::uint32_t)0x80000001 \ + << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0x8; + QTest::newRow("SRLV") << ALU_OP_SRLV \ + << (std::uint32_t)3 \ + << (std::uint32_t)0x80000008 \ + << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0x10000001; + QTest::newRow("SRAV") << ALU_OP_SRAV \ + << (std::uint32_t)3 \ + << (std::uint32_t)0x80000008 \ + << (std::uint8_t)0 \ + << Registers() \ + << Registers() \ + << (std::uint32_t)0xF0000001; + // JR and JALR should have no effect and we test that in core (it really doesn't make sense to test it here) QTest::newRow("MOVZ") << ALU_OP_MOVZ \ << (std::uint32_t)22 \ << (std::uint32_t)0 \ diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index 1e5b502..c38eb26 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -82,7 +82,7 @@ static void core_regs_data() { regs_init.write_gp(24, 0x800000f0); regs_init.write_gp(25, 3); Registers regs_res(regs_init); - regs_res.write_gp(26, 0x8000001e); + regs_res.write_gp(26, 0xF000001e); QTest::newRow("SRA") << Instruction(0, 0, 24, 26, 3, 3) \ << regs_init \ << regs_res; |