aboutsummaryrefslogtreecommitdiff
path: root/qtmips_cli
diff options
context:
space:
mode:
authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-03-31 20:41:05 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-03-31 20:41:05 +0200
commitf936893d4c5be40ebf1c7b6a9341ffce4c82ea03 (patch)
treed58365b9604154c66d202f104469a4094be1ebf3 /qtmips_cli
parent8de3836bee7b844b75564f12b700c323c4f3d53b (diff)
downloadqtmips-f936893d4c5be40ebf1c7b6a9341ffce4c82ea03.tar.gz
qtmips-f936893d4c5be40ebf1c7b6a9341ffce4c82ea03.tar.bz2
qtmips-f936893d4c5be40ebf1c7b6a9341ffce4c82ea03.zip
Set gray background to stalled instructions/idled stages.
This allows to easier identify unused pipeline stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_cli')
-rw-r--r--qtmips_cli/tracer.cpp20
-rw-r--r--qtmips_cli/tracer.h10
2 files changed, 15 insertions, 15 deletions
diff --git a/qtmips_cli/tracer.cpp b/qtmips_cli/tracer.cpp
index 097842c..198ca89 100644
--- a/qtmips_cli/tracer.cpp
+++ b/qtmips_cli/tracer.cpp
@@ -102,24 +102,24 @@ void Tracer::reg_hi() {
r_hi = true;
}
-void Tracer::instruction_fetch(const Instruction &inst, std::uint32_t inst_addr, ExceptionCause excause) {
- cout << "Fetch: " << (excause != EXCAUSE_NONE? "!": "") << inst.to_str(inst_addr).toStdString() << endl;
+void Tracer::instruction_fetch(const Instruction &inst, std::uint32_t inst_addr, ExceptionCause excause, bool valid) {
+ cout << "Fetch: " << (excause != EXCAUSE_NONE? "!": "") << (valid? inst.to_str(inst_addr).toStdString() : "Idle") << endl;
}
-void Tracer::instruction_decode(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause) {
- cout << "Decode: " << (excause != EXCAUSE_NONE? "!": "") << inst.to_str(inst_addr).toStdString() << endl;
+void Tracer::instruction_decode(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause, bool valid) {
+ cout << "Decode: " << (excause != EXCAUSE_NONE? "!": "") << (valid? inst.to_str(inst_addr).toStdString() : "Idle") << endl;
}
-void Tracer::instruction_execute(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause) {
- cout << "Execute: " << (excause != EXCAUSE_NONE? "!": "") << inst.to_str(inst_addr).toStdString() << endl;
+void Tracer::instruction_execute(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause, bool valid) {
+ cout << "Execute: " << (excause != EXCAUSE_NONE? "!": "") << (valid? inst.to_str(inst_addr).toStdString() : "Idle") << endl;
}
-void Tracer::instruction_memory(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause) {
- cout << "Memory: " << (excause != EXCAUSE_NONE? "!": "") << inst.to_str(inst_addr).toStdString() << endl;
+void Tracer::instruction_memory(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause, bool valid) {
+ cout << "Memory: " << (excause != EXCAUSE_NONE? "!": "") << (valid? inst.to_str(inst_addr).toStdString() : "Idle") << endl;
}
-void Tracer::instruction_writeback(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause) {
- cout << "Writeback: " << (excause != EXCAUSE_NONE? "!": "") << inst.to_str(inst_addr).toStdString() << endl;
+void Tracer::instruction_writeback(const machine::Instruction &inst, uint32_t inst_addr, ExceptionCause excause, bool valid) {
+ cout << "Writeback: " << (excause != EXCAUSE_NONE? "!": "") << (valid? inst.to_str(inst_addr).toStdString() : "Idle") << endl;
}
void Tracer::regs_pc_update(std::uint32_t val) {
diff --git a/qtmips_cli/tracer.h b/qtmips_cli/tracer.h
index eefad8e..95af98d 100644
--- a/qtmips_cli/tracer.h
+++ b/qtmips_cli/tracer.h
@@ -57,11 +57,11 @@ public:
void reg_hi();
private slots:
- void instruction_fetch(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause);
- void instruction_decode(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause);
- void instruction_execute(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause);
- void instruction_memory(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause);
- void instruction_writeback(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause);
+ void instruction_fetch(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause, bool valid);
+ void instruction_decode(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause, bool valid);
+ void instruction_execute(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause, bool valid);
+ void instruction_memory(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause, bool valid);
+ void instruction_writeback(const machine::Instruction &inst, uint32_t inst_addr, machine::ExceptionCause excause, bool valid);
void regs_pc_update(std::uint32_t val);
void regs_gp_update(std::uint8_t i, std::uint32_t val);