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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-03-16 21:18:48 +0100 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-03-16 21:18:48 +0100 |
| commit | 7a40807e86aa0d16714a8bf854075c739d52ca40 (patch) | |
| tree | 310831ebc665e6951b7bd352d52f3126b454ea17 /docs | |
| parent | 371e31948fb3bc01359b24a7f325d3e1d149f98b (diff) | |
| download | qtmips-7a40807e86aa0d16714a8bf854075c739d52ca40.tar.gz qtmips-7a40807e86aa0d16714a8bf854075c739d52ca40.tar.bz2 qtmips-7a40807e86aa0d16714a8bf854075c739d52ca40.zip | |
Update readme - include how CACHE and SYNCI instructions are implemented.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/exec-formats-and-tools.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/exec-formats-and-tools.md b/docs/exec-formats-and-tools.md index 85367c5..e2f29f3 100644 --- a/docs/exec-formats-and-tools.md +++ b/docs/exec-formats-and-tools.md @@ -83,8 +83,8 @@ instructions in the pipeline are discarded and execution stops. PC is set to the address of instruction causing the exception or to the branch instruction address if the exception occurs in delay slot. When the single step or continuous execution -is requested again then the "hardware" breakpoint exception -in the fetch stage is masked for the first executed instruction which. +is requested again then the "hardware" breakpoint exception +in the fetch stage is masked for the first executed instruction. But then CPU accepts breakpoint exceptions again. This is why it is not a good idea to set up breakpoint to address of an instruction in the delay slot. |