From 7a40807e86aa0d16714a8bf854075c739d52ca40 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sat, 16 Mar 2019 21:18:48 +0100 Subject: Update readme - include how CACHE and SYNCI instructions are implemented. Signed-off-by: Pavel Pisa --- docs/exec-formats-and-tools.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'docs') diff --git a/docs/exec-formats-and-tools.md b/docs/exec-formats-and-tools.md index 85367c5..e2f29f3 100644 --- a/docs/exec-formats-and-tools.md +++ b/docs/exec-formats-and-tools.md @@ -83,8 +83,8 @@ instructions in the pipeline are discarded and execution stops. PC is set to the address of instruction causing the exception or to the branch instruction address if the exception occurs in delay slot. When the single step or continuous execution -is requested again then the "hardware" breakpoint exception -in the fetch stage is masked for the first executed instruction which. +is requested again then the "hardware" breakpoint exception +in the fetch stage is masked for the first executed instruction. But then CPU accepts breakpoint exceptions again. This is why it is not a good idea to set up breakpoint to address of an instruction in the delay slot. -- cgit v1.2.3