diff options
Diffstat (limited to 'nixos/modules/omnia-kernel-patches')
53 files changed, 5349 insertions, 0 deletions
diff --git a/nixos/modules/omnia-kernel-patches/0001-ARM-dts-kirkwood-Add-definitions-for-PCIe-legacy-INT.patch b/nixos/modules/omnia-kernel-patches/0001-ARM-dts-kirkwood-Add-definitions-for-PCIe-legacy-INT.patch new file mode 100644 index 0000000..8cd0223 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0001-ARM-dts-kirkwood-Add-definitions-for-PCIe-legacy-INT.patch @@ -0,0 +1,161 @@ +From 9e13d337f437e6b6ce55d9767c0e04e8b6dc347e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:14:33 +0200 +Subject: [PATCH 01/53] ARM: dts: kirkwood: Add definitions for PCIe legacy + INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/kirkwood-6192.dtsi | 14 ++++++++++-- + arch/arm/boot/dts/kirkwood-6281.dtsi | 14 ++++++++++-- + arch/arm/boot/dts/kirkwood-6282.dtsi | 28 ++++++++++++++++++++---- + arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 14 ++++++++++-- + 4 files changed, 60 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi +index 396bcba08adb..07f4f7f98c0c 100644 +--- a/arch/arm/boot/dts/kirkwood-6192.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6192.dtsi +@@ -26,12 +26,22 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; ++ interrupt-names = "intx"; ++ interrupts = <9>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; ++ ++ pcie_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi +index faa05849a40d..d08a9a5ecc26 100644 +--- a/arch/arm/boot/dts/kirkwood-6281.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6281.dtsi +@@ -26,12 +26,22 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; ++ interrupt-names = "intx"; ++ interrupts = <9>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; ++ ++ pcie_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi +index e84c54b77dea..2eea5b304f47 100644 +--- a/arch/arm/boot/dts/kirkwood-6282.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6282.dtsi +@@ -30,12 +30,22 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; ++ interrupt-names = "intx"; ++ interrupts = <9>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie0_intc 0>, ++ <0 0 0 2 &pcie0_intc 1>, ++ <0 0 0 3 &pcie0_intc 2>, ++ <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; ++ ++ pcie0_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie1: pcie@2,0 { +@@ -48,12 +58,22 @@ pcie1: pcie@2,0 { + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 10>; ++ interrupt-names = "intx"; ++ interrupts = <10>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +index 299c147298c3..070bc13242b8 100644 +--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi ++++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +@@ -26,12 +26,22 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 9>; ++ interrupt-names = "intx"; ++ interrupts = <9>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; ++ ++ pcie_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0002-ARM-dts-dove-Add-definitions-for-PCIe-legacy-INTx-in.patch b/nixos/modules/omnia-kernel-patches/0002-ARM-dts-dove-Add-definitions-for-PCIe-legacy-INTx-in.patch new file mode 100644 index 0000000..1bde752 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0002-ARM-dts-dove-Add-definitions-for-PCIe-legacy-INTx-in.patch @@ -0,0 +1,63 @@ +From 314b618d623977c7e9eaf52f8e75cbb1b4a98fbb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:17:27 +0200 +Subject: [PATCH 02/53] ARM: dts: dove: Add definitions for PCIe legacy INTx + interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/dove.dtsi | 28 ++++++++++++++++++++++++---- + 1 file changed, 24 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi +index 89e0bdaf3a85..96ba47c061a7 100644 +--- a/arch/arm/boot/dts/dove.dtsi ++++ b/arch/arm/boot/dts/dove.dtsi +@@ -122,8 +122,18 @@ pcie0: pcie@1 { + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 16>; ++ interrupt-names = "intx"; ++ interrupts = <16>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie0_intc 0>, ++ <0 0 0 2 &pcie0_intc 1>, ++ <0 0 0 3 &pcie0_intc 2>, ++ <0 0 0 4 &pcie0_intc 3>; ++ ++ pcie0_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie1: pcie@2 { +@@ -141,8 +151,18 @@ pcie1: pcie@2 { + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &intc 18>; ++ interrupt-names = "intx"; ++ interrupts = <18>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0003-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-leg.patch b/nixos/modules/omnia-kernel-patches/0003-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-leg.patch new file mode 100644 index 0000000..6d5b388 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0003-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-leg.patch @@ -0,0 +1,79 @@ +From 687c6b1e284226ffc8b57dc24b459dd14e29b283 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:24:58 +0200 +Subject: [PATCH 03/53] ARM: dts: armada-370.dtsi: Add definitions for PCIe + legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-370.dtsi | 28 ++++++++++++++++++++++++---- + 1 file changed, 24 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi +index 46e6d3ed8f35..9dc928859ad3 100644 +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -60,16 +60,26 @@ pcie0: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie0_intc 0>, ++ <0 0 0 2 &pcie0_intc 1>, ++ <0 0 0 3 &pcie0_intc 2>, ++ <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie0_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie2: pcie@2,0 { +@@ -78,16 +88,26 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0004-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch b/nixos/modules/omnia-kernel-patches/0004-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch new file mode 100644 index 0000000..7feef6e --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0004-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch @@ -0,0 +1,50 @@ +From e0295c1251d6ed7a1304bf8feba03ecfa36bc736 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:02:23 +0200 +Subject: [PATCH 04/53] ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for + PCIe legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +index 38a052a0312d..b21ffb819b1d 100644 +--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi ++++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +@@ -76,16 +76,26 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0005-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0005-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..2b3192b --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0005-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,166 @@ +From 551835b8474300cd74d67339ab8d6c503abd3347 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 19:26:59 +0200 +Subject: [PATCH 05/53] ARM: dts: armada-xp-mv78230.dtsi: Add definitions for + PCIe legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 70 ++++++++++++++++++++---- + 1 file changed, 60 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +index 8558bf6bb54c..bf9360f41e0a 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -83,16 +83,26 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie2: pcie@2,0 { +@@ -101,16 +111,26 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie3: pcie@3,0 { +@@ -119,16 +139,26 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie4: pcie@4,0 { +@@ -137,16 +167,26 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie4_intc 0>, ++ <0 0 0 2 &pcie4_intc 1>, ++ <0 0 0 3 &pcie4_intc 2>, ++ <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie4_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie5: pcie@5,0 { +@@ -155,16 +195,26 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie5_intc 0>, ++ <0 0 0 2 &pcie5_intc 1>, ++ <0 0 0 3 &pcie5_intc 2>, ++ <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; ++ ++ pcie5_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..4830205 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,282 @@ +From 7231e882cb8da99ebc2e04e28ade32cffecd33d4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 19:54:06 +0200 +Subject: [PATCH 06/53] ARM: dts: armada-xp-mv78260.dtsi: Add definitions for + PCIe legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 126 +++++++++++++++++++---- + 1 file changed, 108 insertions(+), 18 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +index 2d85fe8ac327..0714af52e607 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -98,16 +98,26 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie2: pcie@2,0 { +@@ -116,16 +126,26 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie3: pcie@3,0 { +@@ -134,16 +154,26 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie4: pcie@4,0 { +@@ -152,16 +182,26 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie4_intc 0>, ++ <0 0 0 2 &pcie4_intc 1>, ++ <0 0 0 3 &pcie4_intc 2>, ++ <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie4_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie5: pcie@5,0 { +@@ -170,16 +210,26 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie5_intc 0>, ++ <0 0 0 2 &pcie5_intc 1>, ++ <0 0 0 3 &pcie5_intc 2>, ++ <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; ++ ++ pcie5_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie6: pcie@6,0 { +@@ -188,16 +238,26 @@ pcie6: pcie@6,0 { + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 63>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie6_intc 0>, ++ <0 0 0 2 &pcie6_intc 1>, ++ <0 0 0 3 &pcie6_intc 2>, ++ <0 0 0 4 &pcie6_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; ++ ++ pcie6_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie7: pcie@7,0 { +@@ -206,16 +266,26 @@ pcie7: pcie@7,0 { + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 64>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie7_intc 0>, ++ <0 0 0 2 &pcie7_intc 1>, ++ <0 0 0 3 &pcie7_intc 2>, ++ <0 0 0 4 &pcie7_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; ++ ++ pcie7_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie8: pcie@8,0 { +@@ -224,16 +294,26 @@ pcie8: pcie@8,0 { + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 65>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie8_intc 0>, ++ <0 0 0 2 &pcie8_intc 1>, ++ <0 0 0 3 &pcie8_intc 2>, ++ <0 0 0 4 &pcie8_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; ++ ++ pcie8_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie9: pcie@9,0 { +@@ -242,16 +322,26 @@ pcie9: pcie@9,0 { + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 99>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie9_intc 0>, ++ <0 0 0 2 &pcie9_intc 1>, ++ <0 0 0 3 &pcie9_intc 2>, ++ <0 0 0 4 &pcie9_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; ++ ++ pcie9_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0007-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0007-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..54e3af6 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0007-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,311 @@ +From 0916eafa8f4d52da19b20daf6a1d7637ea08ebfc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 19:58:06 +0200 +Subject: [PATCH 07/53] ARM: dts: armada-xp-mv78460.dtsi: Add definitions for + PCIe legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 140 +++++++++++++++++++---- + 1 file changed, 120 insertions(+), 20 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +index 230a3fd36b30..16185edf9aa5 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -119,16 +119,26 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie2: pcie@2,0 { +@@ -137,16 +147,26 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie3: pcie@3,0 { +@@ -155,16 +175,26 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie4: pcie@4,0 { +@@ -173,16 +203,26 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie4_intc 0>, ++ <0 0 0 2 &pcie4_intc 1>, ++ <0 0 0 3 &pcie4_intc 2>, ++ <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie4_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie5: pcie@5,0 { +@@ -191,16 +231,26 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie5_intc 0>, ++ <0 0 0 2 &pcie5_intc 1>, ++ <0 0 0 3 &pcie5_intc 2>, ++ <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; ++ ++ pcie5_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie6: pcie@6,0 { +@@ -209,16 +259,26 @@ pcie6: pcie@6,0 { + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 63>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie6_intc 0>, ++ <0 0 0 2 &pcie6_intc 1>, ++ <0 0 0 3 &pcie6_intc 2>, ++ <0 0 0 4 &pcie6_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; ++ ++ pcie6_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie7: pcie@7,0 { +@@ -227,16 +287,26 @@ pcie7: pcie@7,0 { + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 64>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie7_intc 0>, ++ <0 0 0 2 &pcie7_intc 1>, ++ <0 0 0 3 &pcie7_intc 2>, ++ <0 0 0 4 &pcie7_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; ++ ++ pcie7_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie8: pcie@8,0 { +@@ -245,16 +315,26 @@ pcie8: pcie@8,0 { + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 65>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie8_intc 0>, ++ <0 0 0 2 &pcie8_intc 1>, ++ <0 0 0 3 &pcie8_intc 2>, ++ <0 0 0 4 &pcie8_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; ++ ++ pcie8_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie9: pcie@9,0 { +@@ -263,16 +343,26 @@ pcie9: pcie@9,0 { + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 99>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie9_intc 0>, ++ <0 0 0 2 &pcie9_intc 1>, ++ <0 0 0 3 &pcie9_intc 2>, ++ <0 0 0 4 &pcie9_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; ++ ++ pcie9_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie10: pcie@a,0 { +@@ -281,16 +371,26 @@ pcie10: pcie@a,0 { + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&mpic 103>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 103>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie10_intc 0>, ++ <0 0 0 2 &pcie10_intc 1>, ++ <0 0 0 3 &pcie10_intc 2>, ++ <0 0 0 4 &pcie10_intc 3>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; ++ ++ pcie10_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0008-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-leg.patch b/nixos/modules/omnia-kernel-patches/0008-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-leg.patch new file mode 100644 index 0000000..30a1d5d --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0008-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-leg.patch @@ -0,0 +1,79 @@ +From 6c7ca0a6c606edf728e4f8734caef77b7edbb18b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:38:11 +0200 +Subject: [PATCH 08/53] ARM: dts: armada-375.dtsi: Add definitions for PCIe + legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-375.dtsi | 28 ++++++++++++++++++++++++---- + 1 file changed, 24 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi +index 7f2f24a29e6c..929deaf312a5 100644 +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -568,16 +568,26 @@ pcie0: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie0_intc 0>, ++ <0 0 0 2 &pcie0_intc 1>, ++ <0 0 0 3 &pcie0_intc 2>, ++ <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie0_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + pcie1: pcie@2,0 { +@@ -586,16 +596,26 @@ pcie1: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + }; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0009-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch b/nixos/modules/omnia-kernel-patches/0009-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch new file mode 100644 index 0000000..2423c80 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0009-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch @@ -0,0 +1,108 @@ +From 86710d3c9c23e57604b5ccf9a08bdc1a844dff8a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:39:06 +0200 +Subject: [PATCH 09/53] ARM: dts: armada-380.dtsi: Add definitions for PCIe + legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-380.dtsi | 42 ++++++++++++++++++++++++++----- + 1 file changed, 36 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi +index cff1269f3fbf..ce1dddb2269b 100644 +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -64,16 +64,26 @@ pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -83,16 +93,26 @@ pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -102,16 +122,26 @@ pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0010-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-leg.patch b/nixos/modules/omnia-kernel-patches/0010-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-leg.patch new file mode 100644 index 0000000..4bff8e4 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0010-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-leg.patch @@ -0,0 +1,137 @@ +From c9edeb10ac82fc2485496c435eed6106ded48537 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:47:53 +0200 +Subject: [PATCH 10/53] ARM: dts: armada-39x.dtsi: Add definitions for PCIe + legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-39x.dtsi | 56 ++++++++++++++++++++++++++----- + 1 file changed, 48 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi +index e0b7c2099831..923b035a3ab3 100644 +--- a/arch/arm/boot/dts/armada-39x.dtsi ++++ b/arch/arm/boot/dts/armada-39x.dtsi +@@ -438,16 +438,26 @@ pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -457,16 +467,26 @@ pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -476,16 +496,26 @@ pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* +@@ -498,16 +528,26 @@ pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie4_intc 0>, ++ <0 0 0 2 &pcie4_intc 1>, ++ <0 0 0 3 &pcie4_intc 2>, ++ <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; ++ ++ pcie4_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0011-dt-bindings-Add-slot-power-limit-milliwatt-PCIe-port.patch b/nixos/modules/omnia-kernel-patches/0011-dt-bindings-Add-slot-power-limit-milliwatt-PCIe-port.patch new file mode 100644 index 0000000..6b72856 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0011-dt-bindings-Add-slot-power-limit-milliwatt-PCIe-port.patch @@ -0,0 +1,46 @@ +From 63b77dea640590a118231dde51cba9003c7eecb5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sun, 31 Oct 2021 16:07:05 +0100 +Subject: [PATCH 11/53] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port + property +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This property specifies slot power limit in mW unit. It is a form-factor +and board specific value and must be initialized by hardware. + +Some PCIe controllers delegate this work to software to allow hardware +flexibility and therefore this property basically specifies what should +host bridge program into PCIe Slot Capabilities registers. + +The property needs to be specified in mW unit instead of the special format +defined by Slot Capabilities (which encodes scaling factor or different +unit). Host drivers should convert the value from mW to needed format. + +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt +index 6a8f2874a24d..b0cc133ed00d 100644 +--- a/Documentation/devicetree/bindings/pci/pci.txt ++++ b/Documentation/devicetree/bindings/pci/pci.txt +@@ -32,6 +32,12 @@ driver implementation may support the following properties: + root port to downstream device and host bridge drivers can do programming + which depends on CLKREQ signal existence. For example, programming root port + not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. ++- slot-power-limit-milliwatt: ++ If present, this property specifies slot power limit in milliwatts. Host ++ drivers can parse this property and use it for programming Root Port or host ++ bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages ++ through the Root Port or host bridge when transitioning PCIe link from a ++ non-DL_Up Status to a DL_Up Status. + + PCI-PCI Bridge properties + ------------------------- +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0012-PCI-pci-bridge-emul-Set-position-of-PCI-capabilities.patch b/nixos/modules/omnia-kernel-patches/0012-PCI-pci-bridge-emul-Set-position-of-PCI-capabilities.patch new file mode 100644 index 0000000..35c1502 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0012-PCI-pci-bridge-emul-Set-position-of-PCI-capabilities.patch @@ -0,0 +1,164 @@ +From cc8f3dbd79c159d03d030658885f8983081d5611 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sun, 3 Jul 2022 12:40:13 +0200 +Subject: [PATCH 12/53] PCI: pci-bridge-emul: Set position of PCI capabilities + to real HW value +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mvebu and aardvark HW have PCIe capabilities on different offset in PCI +config space. Extend pci-bridge-emul.c code to allow setting custom driver +custom value where PCIe capabilities starts. + +With this change PCIe capabilities of both drivers are reported at the same +location as where they are reported by U-Boot - in their real HW offset. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 1 + + drivers/pci/controller/pci-mvebu.c | 1 + + drivers/pci/pci-bridge-emul.c | 48 +++++++++++++++++---------- + drivers/pci/pci-bridge-emul.h | 2 ++ + 4 files changed, 35 insertions(+), 17 deletions(-) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 966c8b48bd96..4834198cc86b 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -1078,6 +1078,7 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) + bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); + + bridge->has_pcie = true; ++ bridge->pcie_start = PCIE_CORE_PCIEXP_CAP; + bridge->data = pcie; + bridge->ops = &advk_pci_bridge_emul_ops; + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index af915c951f06..0fdbb5585fec 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -946,6 +946,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + bridge->subsystem_vendor_id = ssdev_id & 0xffff; + bridge->subsystem_id = ssdev_id >> 16; + bridge->has_pcie = true; ++ bridge->pcie_start = PCIE_CAP_PCIEXP; + bridge->data = port; + bridge->ops = &mvebu_pci_bridge_emul_ops; + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index 9c2ca28e3ecf..9334b2dd4764 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -22,11 +22,7 @@ + + #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF + #define PCI_CAP_SSID_SIZEOF (PCI_SSVID_DEVICE_ID + 2) +-#define PCI_CAP_SSID_START PCI_BRIDGE_CONF_END +-#define PCI_CAP_SSID_END (PCI_CAP_SSID_START + PCI_CAP_SSID_SIZEOF) + #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2) +-#define PCI_CAP_PCIE_START PCI_CAP_SSID_END +-#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF) + + /** + * struct pci_bridge_reg_behavior - register bits behaviors +@@ -324,7 +320,7 @@ pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value) + switch (reg) { + case PCI_CAP_LIST_ID: + *value = PCI_CAP_ID_SSVID | +- (bridge->has_pcie ? (PCI_CAP_PCIE_START << 8) : 0); ++ ((bridge->pcie_start > bridge->ssid_start) ? (bridge->pcie_start << 8) : 0); + return PCI_BRIDGE_EMUL_HANDLED; + + case PCI_SSVID_VENDOR_ID: +@@ -365,18 +361,33 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge, + if (!bridge->pci_regs_behavior) + return -ENOMEM; + +- if (bridge->subsystem_vendor_id) +- bridge->conf.capabilities_pointer = PCI_CAP_SSID_START; +- else if (bridge->has_pcie) +- bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; +- else +- bridge->conf.capabilities_pointer = 0; ++ /* If ssid_start and pcie_start were not specified then choose the lowest possible value. */ ++ if (!bridge->ssid_start && !bridge->pcie_start) { ++ if (bridge->subsystem_vendor_id) ++ bridge->ssid_start = PCI_BRIDGE_CONF_END; ++ if (bridge->has_pcie) ++ bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF; ++ } else if (!bridge->ssid_start && bridge->subsystem_vendor_id) { ++ if (bridge->pcie_start - PCI_BRIDGE_CONF_END >= PCI_CAP_SSID_SIZEOF) ++ bridge->ssid_start = PCI_BRIDGE_CONF_END; ++ else ++ bridge->ssid_start = bridge->pcie_start + PCI_CAP_PCIE_SIZEOF; ++ } else if (!bridge->pcie_start && bridge->has_pcie) { ++ if (bridge->ssid_start - PCI_BRIDGE_CONF_END >= PCI_CAP_PCIE_SIZEOF) ++ bridge->pcie_start = PCI_BRIDGE_CONF_END; ++ else ++ bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF; ++ } ++ ++ bridge->conf.capabilities_pointer = min(bridge->ssid_start, bridge->pcie_start); + + if (bridge->conf.capabilities_pointer) + bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); + + if (bridge->has_pcie) { + bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; ++ bridge->pcie_conf.next = (bridge->ssid_start > bridge->pcie_start) ? ++ bridge->ssid_start : 0; + bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); + bridge->pcie_cap_regs_behavior = + kmemdup(pcie_cap_regs_behavior, +@@ -459,15 +470,17 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + read_op = bridge->ops->read_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; +- } else if (reg >= PCI_CAP_SSID_START && reg < PCI_CAP_SSID_END && bridge->subsystem_vendor_id) { ++ } else if (reg >= bridge->ssid_start && reg < bridge->ssid_start + PCI_CAP_SSID_SIZEOF && ++ bridge->subsystem_vendor_id) { + /* Emulated PCI Bridge Subsystem Vendor ID capability */ +- reg -= PCI_CAP_SSID_START; ++ reg -= bridge->ssid_start; + read_op = pci_bridge_emul_read_ssid; + cfgspace = NULL; + behavior = NULL; +- } else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) { ++ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && ++ bridge->has_pcie) { + /* Our emulated PCIe capability */ +- reg -= PCI_CAP_PCIE_START; ++ reg -= bridge->pcie_start; + read_op = bridge->ops->read_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; +@@ -538,9 +551,10 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + write_op = bridge->ops->write_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; +- } else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) { ++ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && ++ bridge->has_pcie) { + /* Our emulated PCIe capability */ +- reg -= PCI_CAP_PCIE_START; ++ reg -= bridge->pcie_start; + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; +diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h +index 71392b67471d..2a0e59c7f0d9 100644 +--- a/drivers/pci/pci-bridge-emul.h ++++ b/drivers/pci/pci-bridge-emul.h +@@ -131,6 +131,8 @@ struct pci_bridge_emul { + struct pci_bridge_reg_behavior *pci_regs_behavior; + struct pci_bridge_reg_behavior *pcie_cap_regs_behavior; + void *data; ++ u8 pcie_start; ++ u8 ssid_start; + bool has_pcie; + u16 subsystem_vendor_id; + u16 subsystem_id; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0013-irqchip-armada-370-xp-Do-not-allow-mapping-IRQ-0-and.patch b/nixos/modules/omnia-kernel-patches/0013-irqchip-armada-370-xp-Do-not-allow-mapping-IRQ-0-and.patch new file mode 100644 index 0000000..ba98b90 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0013-irqchip-armada-370-xp-Do-not-allow-mapping-IRQ-0-and.patch @@ -0,0 +1,37 @@ +From 6d749fdb99d85a7a8e425d9fa1f5a9b8c592478c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sun, 17 Apr 2022 22:56:55 +0200 +Subject: [PATCH 13/53] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +IRQs 0 and 1 cannot be mapped, they are handled internally by this driver +and this driver does not call generic_handle_domain_irq() for these IRQs. +So do not allow mapping these IRQs and correctly propagate error from the +.irq_map callback. + +Signed-off-by: Pali Rohár <pali@kernel.org> +Cc: stable@vger.kernel.org +--- + drivers/irqchip/irq-armada-370-xp.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c +index ee18eb3e72b7..ab02b44a3b4e 100644 +--- a/drivers/irqchip/irq-armada-370-xp.c ++++ b/drivers/irqchip/irq-armada-370-xp.c +@@ -567,6 +567,10 @@ static struct irq_chip armada_370_xp_irq_chip = { + static int armada_370_xp_mpic_irq_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) + { ++ /* IRQs 0 and 1 cannot be mapped, they are handled internally */ ++ if (hw <= 1) ++ return -EINVAL; ++ + armada_370_xp_irq_mask(irq_get_irq_data(virq)); + if (!is_percpu_irq(hw)) + writel(hw, per_cpu_int_base + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0014-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch b/nixos/modules/omnia-kernel-patches/0014-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch new file mode 100644 index 0000000..cf28b6d --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0014-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch @@ -0,0 +1,99 @@ +From 839a63531d3806ae44f5c9daa2c911dc92062ae2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Tue, 24 May 2022 13:57:37 +0200 +Subject: [PATCH 14/53] PCI: mvebu: Use devm_request_irq() for registering + interrupt handler +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Same as in commit a3b69dd0ad62 ("Revert "PCI: aardvark: Rewrite IRQ code to +chained IRQ handler"") for pci-aardvark driver, use devm_request_irq() +instead of chained IRQ handler in pci-mvebu.c driver. + +This change fixes affinity support and allows to pin interrupts from +different PCIe controllers to different CPU cores. + +Fixes: ec075262648f ("PCI: mvebu: Implement support for legacy INTx interrupts") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 30 +++++++++++++++++------------- + 1 file changed, 17 insertions(+), 13 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 0fdbb5585fec..d31f7f3c0c94 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -1090,16 +1090,13 @@ static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) + return 0; + } + +-static void mvebu_pcie_irq_handler(struct irq_desc *desc) ++static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg) + { +- struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc); +- struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct mvebu_pcie_port *port = arg; + struct device *dev = &port->pcie->pdev->dev; + u32 cause, unmask, status; + int i; + +- chained_irq_enter(chip, desc); +- + cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF); + unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); + status = cause & unmask; +@@ -1113,7 +1110,7 @@ static void mvebu_pcie_irq_handler(struct irq_desc *desc) + dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A'); + } + +- chained_irq_exit(chip, desc); ++ return status ? IRQ_HANDLED : IRQ_NONE; + } + + static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +@@ -1571,9 +1568,20 @@ static int mvebu_pcie_probe(struct platform_device *pdev) + mvebu_pcie_powerdown(port); + continue; + } +- irq_set_chained_handler_and_data(irq, +- mvebu_pcie_irq_handler, +- port); ++ ++ ret = devm_request_irq(dev, irq, mvebu_pcie_irq_handler, ++ IRQF_SHARED | IRQF_NO_THREAD, ++ port->name, port); ++ if (ret) { ++ dev_err(dev, "%s: cannot register interrupt handler: %d\n", ++ port->name, ret); ++ irq_domain_remove(port->intx_irq_domain); ++ pci_bridge_emul_cleanup(&port->bridge); ++ devm_iounmap(dev, port->base); ++ port->base = NULL; ++ mvebu_pcie_powerdown(port); ++ continue; ++ } + } + + /* +@@ -1680,7 +1688,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev) + + for (i = 0; i < pcie->nports; i++) { + struct mvebu_pcie_port *port = &pcie->ports[i]; +- int irq = port->intx_irq; + + if (!port->base) + continue; +@@ -1696,9 +1703,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev) + /* Clear all interrupt causes. */ + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); + +- if (irq > 0) +- irq_set_chained_handler_and_data(irq, NULL, NULL); +- + /* Remove IRQ domains. */ + if (port->intx_irq_domain) + irq_domain_remove(port->intx_irq_domain); +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0015-PCI-mvebu-Dispose-INTx-irqs-prior-to-removing-INTx-d.patch b/nixos/modules/omnia-kernel-patches/0015-PCI-mvebu-Dispose-INTx-irqs-prior-to-removing-INTx-d.patch new file mode 100644 index 0000000..d1091c2 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0015-PCI-mvebu-Dispose-INTx-irqs-prior-to-removing-INTx-d.patch @@ -0,0 +1,47 @@ +From 4bf4ddf8cca4ec17a92797d652fb930dbd66cd18 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sat, 9 Jul 2022 16:12:40 +0200 +Subject: [PATCH 15/53] PCI: mvebu: Dispose INTx irqs prior to removing INTx + domain +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Documentation for irq_domain_remove() says that all mapping within the +domain must be disposed prior to domain remove. + +Currently INTx irqs are not disposed in pci-mvebu.c device unbind callback +which cause that kernel crashes after unloading driver and trying to read +/sys/kernel/debug/irq/irqs/<num> or /proc/interrupts. + +Fixes: ec075262648f ("PCI: mvebu: Implement support for legacy INTx interrupts") +Reported-by: Hajo Noerenberg <hajo-linux-bugzilla@noerenberg.de> +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index d31f7f3c0c94..7b0dcdd85cb8 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -1704,8 +1704,15 @@ static int mvebu_pcie_remove(struct platform_device *pdev) + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); + + /* Remove IRQ domains. */ +- if (port->intx_irq_domain) ++ if (port->intx_irq_domain) { ++ int virq, j; ++ for (j = 0; j < PCI_NUM_INTX; j++) { ++ virq = irq_find_mapping(port->intx_irq_domain, j); ++ if (virq > 0) ++ irq_dispose_mapping(virq); ++ } + irq_domain_remove(port->intx_irq_domain); ++ } + + /* Free config space for emulated root bridge. */ + pci_bridge_emul_cleanup(&port->bridge); +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0016-PCI-Assign-PCI-domain-by-ida_alloc.patch b/nixos/modules/omnia-kernel-patches/0016-PCI-Assign-PCI-domain-by-ida_alloc.patch new file mode 100644 index 0000000..a349fb1 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0016-PCI-Assign-PCI-domain-by-ida_alloc.patch @@ -0,0 +1,215 @@ +From 07414acbdce72901154b39226c8707b5a92565b7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sat, 2 Jul 2022 21:37:51 +0200 +Subject: [PATCH 16/53] PCI: Assign PCI domain by ida_alloc() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace assignment of PCI domain from atomic_inc_return() to ida_alloc(). + +Use two IDAs, one for static domain allocations (those which are defined in +device tree) and second for dynamic allocations (all other). + +During removal of root bus / host bridge release also allocated domain id. +So released id can be reused again, for example in situation when +dynamically loading and unloading native PCI host bridge drivers. + +This change also allows to mix static device tree assignment and dynamic by +kernel as all static allocations are reserved in dynamic pool. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/pci.c | 103 +++++++++++++++++++++++++------------------ + drivers/pci/probe.c | 5 +++ + drivers/pci/remove.c | 6 +++ + include/linux/pci.h | 1 + + 4 files changed, 72 insertions(+), 43 deletions(-) + +diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c +index 95bc329e74c0..4589ad52e4ca 100644 +--- a/drivers/pci/pci.c ++++ b/drivers/pci/pci.c +@@ -6758,60 +6758,70 @@ static void pci_no_domains(void) + } + + #ifdef CONFIG_PCI_DOMAINS_GENERIC +-static atomic_t __domain_nr = ATOMIC_INIT(-1); ++static DEFINE_IDA(pci_domain_nr_static_ida); ++static DEFINE_IDA(pci_domain_nr_dynamic_ida); + +-static int pci_get_new_domain_nr(void) ++static void of_pci_reserve_static_domain_nr(void) + { +- return atomic_inc_return(&__domain_nr); ++ struct device_node *np; ++ int domain_nr; ++ ++ for_each_node_by_type(np, "pci") { ++ domain_nr = of_get_pci_domain_nr(np); ++ if (domain_nr < 0) ++ continue; ++ /* ++ * Permanently allocate domain_nr in dynamic_ida ++ * to prevent it from dynamic allocation. ++ */ ++ ida_alloc_range(&pci_domain_nr_dynamic_ida, ++ domain_nr, domain_nr, GFP_KERNEL); ++ } + } + + static int of_pci_bus_find_domain_nr(struct device *parent) + { +- static int use_dt_domains = -1; +- int domain = -1; ++ static bool static_domains_reserved = false; ++ int domain_nr; + +- if (parent) +- domain = of_get_pci_domain_nr(parent->of_node); ++ /* On the first call scan device tree for static allocations. */ ++ if (!static_domains_reserved) { ++ of_pci_reserve_static_domain_nr(); ++ static_domains_reserved = true; ++ } ++ ++ if (parent) { ++ /* ++ * If domain is in DT then allocate it in static IDA. ++ * This prevent duplicate static allocations in case ++ * of errors in DT. ++ */ ++ domain_nr = of_get_pci_domain_nr(parent->of_node); ++ if (domain_nr >= 0) ++ return ida_alloc_range(&pci_domain_nr_static_ida, ++ domain_nr, domain_nr, ++ GFP_KERNEL); ++ } + + /* +- * Check DT domain and use_dt_domains values. +- * +- * If DT domain property is valid (domain >= 0) and +- * use_dt_domains != 0, the DT assignment is valid since this means +- * we have not previously allocated a domain number by using +- * pci_get_new_domain_nr(); we should also update use_dt_domains to +- * 1, to indicate that we have just assigned a domain number from +- * DT. +- * +- * If DT domain property value is not valid (ie domain < 0), and we +- * have not previously assigned a domain number from DT +- * (use_dt_domains != 1) we should assign a domain number by +- * using the: +- * +- * pci_get_new_domain_nr() +- * +- * API and update the use_dt_domains value to keep track of method we +- * are using to assign domain numbers (use_dt_domains = 0). +- * +- * All other combinations imply we have a platform that is trying +- * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), +- * which is a recipe for domain mishandling and it is prevented by +- * invalidating the domain value (domain = -1) and printing a +- * corresponding error. ++ * If domain was not specified in DT then choose free id from dynamic ++ * allocations. All domain numbers from DT are permanently in dynamic ++ * allocations to prevent assigning them to other DT nodes without ++ * static domain. + */ +- if (domain >= 0 && use_dt_domains) { +- use_dt_domains = 1; +- } else if (domain < 0 && use_dt_domains != 1) { +- use_dt_domains = 0; +- domain = pci_get_new_domain_nr(); +- } else { +- if (parent) +- pr_err("Node %pOF has ", parent->of_node); +- pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); +- domain = -1; +- } ++ return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL); ++} + +- return domain; ++static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent) ++{ ++ if (bus->domain_nr < 0) ++ return; ++ ++ /* Release domain from ida in which was it allocated. */ ++ if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr) ++ ida_free(&pci_domain_nr_static_ida, bus->domain_nr); ++ else ++ ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr); + } + + int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) +@@ -6819,6 +6829,13 @@ int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) + return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : + acpi_pci_bus_find_domain_nr(bus); + } ++ ++void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent) ++{ ++ if (!acpi_disabled) ++ return; ++ of_pci_bus_release_domain_nr(bus, parent); ++} + #endif + + /** +diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c +index c5286b027f00..a8db8bf0f196 100644 +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -906,6 +906,8 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge) + bus->domain_nr = pci_bus_find_domain_nr(bus, parent); + else + bus->domain_nr = bridge->domain_nr; ++ if (bus->domain_nr < 0) ++ goto free; + #endif + + b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); +@@ -1030,6 +1032,9 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge) + device_del(&bridge->dev); + + free: ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++ pci_bus_release_domain_nr(bus, parent); ++#endif + kfree(bus); + return err; + } +diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c +index 4c54c75050dc..0145aef1b930 100644 +--- a/drivers/pci/remove.c ++++ b/drivers/pci/remove.c +@@ -160,6 +160,12 @@ void pci_remove_root_bus(struct pci_bus *bus) + pci_remove_bus(bus); + host_bridge->bus = NULL; + ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++ /* Release domain_nr if it was dynamically allocated */ ++ if (host_bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) ++ pci_bus_release_domain_nr(bus, host_bridge->dev.parent); ++#endif ++ + /* remove the host bridge */ + device_del(&host_bridge->dev); + } +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 060af91bafcd..c7abe91899d2 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1723,6 +1723,7 @@ static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) + { return 0; } + #endif + int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); ++void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); + #endif + + /* Some architectures require additional setup to direct VGA traffic */ +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0017-PCI-mvebu-Fix-endianity-when-accessing-pci-emul-brid.patch b/nixos/modules/omnia-kernel-patches/0017-PCI-mvebu-Fix-endianity-when-accessing-pci-emul-brid.patch new file mode 100644 index 0000000..bcd76ff --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0017-PCI-mvebu-Fix-endianity-when-accessing-pci-emul-brid.patch @@ -0,0 +1,68 @@ +From 813ff9e97d2ff664d0d7dba7a1298127aab9d996 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 12 Aug 2022 11:09:11 +0200 +Subject: [PATCH 17/53] PCI: mvebu: Fix endianity when accessing pci emul + bridge members +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PCI emul bridge members iolimitupper, iobaseupper, memlimit and membase are +of type __le16, so correctly access these members via le16_to_cpu() macros. + +Fixes: 4ded69473adb ("PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers") +Reported-by: kernel test robot <lkp@intel.com> +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 7b0dcdd85cb8..28288837dd1f 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -523,7 +523,7 @@ static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) + + /* Are the new iobase/iolimit values invalid? */ + if (conf->iolimit < conf->iobase || +- conf->iolimitupper < conf->iobaseupper) ++ le16_to_cpu(conf->iolimitupper) < le16_to_cpu(conf->iobaseupper)) + return mvebu_pcie_set_window(port, port->io_target, port->io_attr, + &desired, &port->iowin); + +@@ -535,10 +535,10 @@ static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) + * is the CPU address. + */ + desired.remap = ((conf->iobase & 0xF0) << 8) | +- (conf->iobaseupper << 16); ++ (le16_to_cpu(conf->iobaseupper) << 16); + desired.base = port->pcie->io.start + desired.remap; + desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) | +- (conf->iolimitupper << 16)) - ++ (le16_to_cpu(conf->iolimitupper) << 16)) - + desired.remap) + + 1; + +@@ -552,7 +552,7 @@ static int mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) + struct pci_bridge_emul_conf *conf = &port->bridge.conf; + + /* Are the new membase/memlimit values invalid? */ +- if (conf->memlimit < conf->membase) ++ if (le16_to_cpu(conf->memlimit) < le16_to_cpu(conf->membase)) + return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, + &desired, &port->memwin); + +@@ -562,8 +562,8 @@ static int mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) + * window to setup, according to the PCI-to-PCI bridge + * specifications. + */ +- desired.base = ((conf->membase & 0xFFF0) << 16); +- desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) - ++ desired.base = ((le16_to_cpu(conf->membase) & 0xFFF0) << 16); ++ desired.size = (((le16_to_cpu(conf->memlimit) & 0xFFF0) << 16) | 0xFFFFF) - + desired.base + 1; + + return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0018-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch b/nixos/modules/omnia-kernel-patches/0018-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch new file mode 100644 index 0000000..e1f9836 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0018-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch @@ -0,0 +1,35 @@ +From a060615093dd1ad6b372d15f8017b147dc413d5f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 17 Aug 2022 23:46:32 +0200 +Subject: [PATCH 18/53] ARM: dts: dove: Fix assigned-addresses for every PCIe + Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 74ecaa403a74 ("ARM: dove: add PCIe controllers to SoC DT") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/dove.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi +index 96ba47c061a7..70d45d2b1258 100644 +--- a/arch/arm/boot/dts/dove.dtsi ++++ b/arch/arm/boot/dts/dove.dtsi +@@ -139,7 +139,7 @@ pcie0_intc: interrupt-controller { + pcie1: pcie@2 { + device_type = "pci"; + status = "disabled"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0019-ARM-dts-armada-370-Fix-assigned-addresses-for-every-.patch b/nixos/modules/omnia-kernel-patches/0019-ARM-dts-armada-370-Fix-assigned-addresses-for-every-.patch new file mode 100644 index 0000000..d8fe807 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0019-ARM-dts-armada-370-Fix-assigned-addresses-for-every-.patch @@ -0,0 +1,35 @@ +From ffede421c1945bd5d38f1d7641c9902f7ee18923 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 18 Aug 2022 00:01:14 +0200 +Subject: [PATCH 19/53] ARM: dts: armada-370: Fix assigned-addresses for every + PCIe Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: a09a0b7c6ff1 ("arm: mvebu: add PCIe Device Tree informations for Armada 370") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-370.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi +index 9dc928859ad3..2013a5ccecd3 100644 +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -84,7 +84,7 @@ pcie0_intc: interrupt-controller { + + pcie2: pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0020-ARM-dts-armada-xp-Fix-assigned-addresses-for-every-P.patch b/nixos/modules/omnia-kernel-patches/0020-ARM-dts-armada-xp-Fix-assigned-addresses-for-every-P.patch new file mode 100644 index 0000000..9f3ae67 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0020-ARM-dts-armada-xp-Fix-assigned-addresses-for-every-P.patch @@ -0,0 +1,141 @@ +From 6ea68cfd38e5a3752ac4c870894a1389f5c52366 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 18 Aug 2022 00:01:47 +0200 +Subject: [PATCH 20/53] ARM: dts: armada-xp: Fix assigned-addresses for every + PCIe Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 9d8f44f02d4a ("arm: mvebu: add PCIe Device Tree informations for Armada XP") +Fixes: 12b69a599745 ("ARM: mvebu: second PCIe unit of Armada XP mv78230 is only x1 capable") +Fixes: 2163e61c92d9 ("ARM: mvebu: fix second and third PCIe unit of Armada XP mv78260") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 8 ++++---- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 ++++++++-------- + 2 files changed, 12 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +index bf9360f41e0a..5ea9d509cd30 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -107,7 +107,7 @@ pcie1_intc: interrupt-controller { + + pcie2: pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -135,7 +135,7 @@ pcie2_intc: interrupt-controller { + + pcie3: pcie@3,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -163,7 +163,7 @@ pcie3_intc: interrupt-controller { + + pcie4: pcie@4,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; ++ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -191,7 +191,7 @@ pcie4_intc: interrupt-controller { + + pcie5: pcie@5,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; ++ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +index 0714af52e607..6c6fbb9faf5a 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -122,7 +122,7 @@ pcie1_intc: interrupt-controller { + + pcie2: pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -150,7 +150,7 @@ pcie2_intc: interrupt-controller { + + pcie3: pcie@3,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -178,7 +178,7 @@ pcie3_intc: interrupt-controller { + + pcie4: pcie@4,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; ++ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -206,7 +206,7 @@ pcie4_intc: interrupt-controller { + + pcie5: pcie@5,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; ++ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -234,7 +234,7 @@ pcie5_intc: interrupt-controller { + + pcie6: pcie@6,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; ++ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -262,7 +262,7 @@ pcie6_intc: interrupt-controller { + + pcie7: pcie@7,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; ++ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -290,7 +290,7 @@ pcie7_intc: interrupt-controller { + + pcie8: pcie@8,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; ++ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -318,7 +318,7 @@ pcie8_intc: interrupt-controller { + + pcie9: pcie@9,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; ++ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0021-ARM-dts-armada-375-Fix-assigned-addresses-for-every-.patch b/nixos/modules/omnia-kernel-patches/0021-ARM-dts-armada-375-Fix-assigned-addresses-for-every-.patch new file mode 100644 index 0000000..243acad --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0021-ARM-dts-armada-375-Fix-assigned-addresses-for-every-.patch @@ -0,0 +1,35 @@ +From d08dee00c22a7b4ef5c25d59d26d73065325031c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 18 Aug 2022 00:02:33 +0200 +Subject: [PATCH 21/53] ARM: dts: armada-375: Fix assigned-addresses for every + PCIe Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 4de59085091f ("ARM: mvebu: add Device Tree description of the Armada 375 SoC") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-375.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi +index 929deaf312a5..c310ef26d1cc 100644 +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -592,7 +592,7 @@ pcie0_intc: interrupt-controller { + + pcie1: pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0022-ARM-dts-armada-38x-Fix-assigned-addresses-for-every-.patch b/nixos/modules/omnia-kernel-patches/0022-ARM-dts-armada-38x-Fix-assigned-addresses-for-every-.patch new file mode 100644 index 0000000..f39bcc0 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0022-ARM-dts-armada-38x-Fix-assigned-addresses-for-every-.patch @@ -0,0 +1,76 @@ +From 7af2e69f71506deba66b511710473721be9cc78c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 18 Aug 2022 00:03:45 +0200 +Subject: [PATCH 22/53] ARM: dts: armada-38x: Fix assigned-addresses for every + PCIe Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 0d3d96ab0059 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-380.dtsi | 4 ++-- + arch/arm/boot/dts/armada-385.dtsi | 6 +++--- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi +index ce1dddb2269b..e94f22b0e9b5 100644 +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -89,7 +89,7 @@ pcie1_intc: interrupt-controller { + /* x1 port */ + pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -118,7 +118,7 @@ pcie2_intc: interrupt-controller { + /* x1 port */ + pcie@3,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi +index 83392b92dae2..be8d607c59b2 100644 +--- a/arch/arm/boot/dts/armada-385.dtsi ++++ b/arch/arm/boot/dts/armada-385.dtsi +@@ -93,7 +93,7 @@ pcie1_intc: interrupt-controller { + /* x1 port */ + pcie2: pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -121,7 +121,7 @@ pcie2_intc: interrupt-controller { + /* x1 port */ + pcie3: pcie@3,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -152,7 +152,7 @@ pcie3_intc: interrupt-controller { + */ + pcie4: pcie@4,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0023-ARM-dts-armada-39x-Fix-assigned-addresses-for-every-.patch b/nixos/modules/omnia-kernel-patches/0023-ARM-dts-armada-39x-Fix-assigned-addresses-for-every-.patch new file mode 100644 index 0000000..fe081f0 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0023-ARM-dts-armada-39x-Fix-assigned-addresses-for-every-.patch @@ -0,0 +1,53 @@ +From 649dc5313d713a43622e75d89b776042828489e6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 18 Aug 2022 00:04:33 +0200 +Subject: [PATCH 23/53] ARM: dts: armada-39x: Fix assigned-addresses for every + PCIe Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 538da83ddbea ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-39x.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi +index 923b035a3ab3..9d1cac49c022 100644 +--- a/arch/arm/boot/dts/armada-39x.dtsi ++++ b/arch/arm/boot/dts/armada-39x.dtsi +@@ -463,7 +463,7 @@ pcie1_intc: interrupt-controller { + /* x1 port */ + pcie@2,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -492,7 +492,7 @@ pcie2_intc: interrupt-controller { + /* x1 port */ + pcie@3,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -524,7 +524,7 @@ pcie3_intc: interrupt-controller { + */ + pcie@4,0 { + device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0024-irqchip-armada-370-xp-Do-not-touch-IPI-registers-on-.patch b/nixos/modules/omnia-kernel-patches/0024-irqchip-armada-370-xp-Do-not-touch-IPI-registers-on-.patch new file mode 100644 index 0000000..8574d75 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0024-irqchip-armada-370-xp-Do-not-touch-IPI-registers-on-.patch @@ -0,0 +1,67 @@ +From ee17678fb1697d33a40aaff502d191ef111972d3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Thu, 11 Aug 2022 11:35:53 +0200 +Subject: [PATCH 24/53] irqchip/armada-370-xp: Do not touch IPI registers on + platforms without IPI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +IPI is used only when we do not have parent irq. On platforms with parent +irq are those IPI registers used for additional set of MSI interrupts +(which are currently unused). So do not touch these registers when IPI is +not used. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/irqchip/irq-armada-370-xp.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c +index ab02b44a3b4e..f550d8af96e3 100644 +--- a/drivers/irqchip/irq-armada-370-xp.c ++++ b/drivers/irqchip/irq-armada-370-xp.c +@@ -497,6 +497,10 @@ static void armada_xp_mpic_smp_cpu_init(void) + for (i = 0; i < nr_irqs; i++) + writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); + ++ /* IPI is not used when we do have parent irq */ ++ if (parent_irq > 0) ++ return; ++ + /* Disable all IPIs */ + writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + +@@ -746,7 +750,8 @@ static void armada_370_xp_mpic_resume(void) + /* Reconfigure doorbells for IPIs and MSIs */ + writel(doorbell_mask_reg, + per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); +- if (doorbell_mask_reg & IPI_DOORBELL_MASK) ++ /* IPI is used only when we do not have parent irq */ ++ if (parent_irq <= 0 && (doorbell_mask_reg & IPI_DOORBELL_MASK)) + writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) + writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); +@@ -796,13 +801,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, + BUG_ON(!armada_370_xp_mpic_domain); + irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED); + ++ /* ++ * parent_irq is used for distinguish between IPI and non-IPI platforms. ++ * So initialize it before calling any other driver functions. ++ */ ++ parent_irq = irq_of_parse_and_map(node, 0); ++ + /* Setup for the boot CPU */ + armada_xp_mpic_perf_init(); + armada_xp_mpic_smp_cpu_init(); + + armada_370_xp_msi_init(node, main_int_res.start); + +- parent_irq = irq_of_parse_and_map(node, 0); + if (parent_irq <= 0) { + irq_set_default_host(armada_370_xp_mpic_domain); + set_handle_irq(armada_370_xp_handle_irq); +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0025-dt-bindings-PCI-mvebu-Update-information-about-error.patch b/nixos/modules/omnia-kernel-patches/0025-dt-bindings-PCI-mvebu-Update-information-about-error.patch new file mode 100644 index 0000000..06e09ae --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0025-dt-bindings-PCI-mvebu-Update-information-about-error.patch @@ -0,0 +1,32 @@ +From 713e7fc14be5c926a7cc0f9240949152bbb7fc2c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Tue, 2 Nov 2021 11:06:18 +0100 +Subject: [PATCH 25/53] dt-bindings: PCI: mvebu: Update information about error + interrupt +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mvebu error interrupt is triggered by any non-intx event, which is mainly +some pcie error. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + Documentation/devicetree/bindings/pci/mvebu-pci.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +index 6d022a9d36ee..8f0bca42113f 100644 +--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt ++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +@@ -83,6 +83,7 @@ and the following optional properties: + specified will default to 100ms, as required by the PCIe specification. + - interrupt-names: list of interrupt names, supported are: + - "intx" - interrupt line triggered by one of the legacy interrupt ++ - "error" - interrupt line triggered by any other event (non-intx) + - interrupts or interrupts-extended: List of the interrupt sources which + corresponding to the "interrupt-names". If non-empty then also additional + 'interrupt-controller' subnode must be defined. +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0026-PCI-mvebu-Implement-support-for-interrupts-on-emulat.patch b/nixos/modules/omnia-kernel-patches/0026-PCI-mvebu-Implement-support-for-interrupts-on-emulat.patch new file mode 100644 index 0000000..1a64f40 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0026-PCI-mvebu-Implement-support-for-interrupts-on-emulat.patch @@ -0,0 +1,437 @@ +From 522b193353b57c4006c77f2a5229e39d1f411aef Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 17 Sep 2021 14:40:17 +0200 +Subject: [PATCH 26/53] PCI: mvebu: Implement support for interrupts on + emulated bridge +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds support for PME and ERR interrupts reported by emulated bridge +(for PME and AER kernel drivers) via new Root Port irq chip as these +interrupts from PCIe Root Ports are handled by mvebu hardware completely +separately from INTx and MSI interrupts send by real PCIe devices. + +With this change, kernel PME and AER drivers start working as they can +acquire required interrupt lines (provided by mvebu rp virtual irq chip). + +Note that for this support, device tree files has to be properly adjusted +to provide "interrupts" or "interrupts-extended" property with error +interrupt source and "interrupt-names" property with "error" string. + +If device tree files do not provide these properties then driver would work +as before and would not provide interrupts on emulated bridge, like before. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 256 ++++++++++++++++++++++++++--- + 1 file changed, 237 insertions(+), 19 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 28288837dd1f..ddd5ba8b265e 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -56,8 +56,16 @@ + #define PCIE_CONF_DATA_OFF 0x18fc + #define PCIE_INT_CAUSE_OFF 0x1900 + #define PCIE_INT_UNMASK_OFF 0x1910 ++#define PCIE_INT_DET_COR BIT(8) ++#define PCIE_INT_DET_NONFATAL BIT(9) ++#define PCIE_INT_DET_FATAL BIT(10) ++#define PCIE_INT_ERR_FATAL BIT(16) ++#define PCIE_INT_ERR_NONFATAL BIT(17) ++#define PCIE_INT_ERR_COR BIT(18) + #define PCIE_INT_INTX(i) BIT(24+i) + #define PCIE_INT_PM_PME BIT(28) ++#define PCIE_INT_DET_MASK (PCIE_INT_DET_COR | PCIE_INT_DET_NONFATAL | PCIE_INT_DET_FATAL) ++#define PCIE_INT_ERR_MASK (PCIE_INT_ERR_FATAL | PCIE_INT_ERR_NONFATAL | PCIE_INT_ERR_COR) + #define PCIE_INT_ALL_MASK GENMASK(31, 0) + #define PCIE_CTRL_OFF 0x1a00 + #define PCIE_CTRL_X1_MODE 0x0001 +@@ -120,9 +128,12 @@ struct mvebu_pcie_port { + struct resource regs; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; ++ struct irq_domain *rp_irq_domain; + struct irq_domain *intx_irq_domain; + raw_spinlock_t irq_lock; ++ int error_irq; + int intx_irq; ++ bool pme_pending; + }; + + static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) +@@ -321,9 +332,19 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) + /* Clear all interrupt causes. */ + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); + +- /* Check if "intx" interrupt was specified in DT. */ +- if (port->intx_irq > 0) +- return; ++ /* ++ * Unmask all error interrupts which are internally generated. ++ * They cannot be disabled by SERR# Enable bit in PCI Command register, ++ * see Figure 6-3: Pseudo Logic Diagram for Error Message Controls in ++ * PCIe base specification. ++ * Internally generated mvebu interrupts are reported via mvebu summary ++ * interrupt which requires "error" interrupt to be specified in DT. ++ */ ++ if (port->error_irq > 0) { ++ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ unmask |= PCIE_INT_DET_MASK; ++ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ } + + /* + * Fallback code when "intx" interrupt was not specified in DT: +@@ -335,10 +356,12 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) + * performance penalty as every PCIe interrupt handler needs to be + * called when some interrupt is triggered. + */ +- unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); +- unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | +- PCIE_INT_INTX(2) | PCIE_INT_INTX(3); +- mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ if (port->intx_irq <= 0) { ++ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | ++ PCIE_INT_INTX(2) | PCIE_INT_INTX(3); ++ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ } + } + + static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, +@@ -598,11 +621,16 @@ mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, + case PCI_INTERRUPT_LINE: { + /* + * From the whole 32bit register we support reading from HW only +- * one bit: PCI_BRIDGE_CTL_BUS_RESET. ++ * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR. + * Other bits are retrieved only from emulated config buffer. + */ + __le32 *cfgspace = (__le32 *)&bridge->conf; + u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); ++ if ((mvebu_readl(port, PCIE_INT_UNMASK_OFF) & ++ PCIE_INT_ERR_MASK) == PCIE_INT_ERR_MASK) ++ val |= PCI_BRIDGE_CTL_SERR << 16; ++ else ++ val &= ~(PCI_BRIDGE_CTL_SERR << 16); + if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET) + val |= PCI_BRIDGE_CTL_BUS_RESET << 16; + else +@@ -670,6 +698,11 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + break; + } + ++ case PCI_EXP_RTCTL: ++ *value = (mvebu_readl(port, PCIE_INT_UNMASK_OFF) & ++ PCIE_INT_PM_PME) ? PCI_EXP_RTCTL_PMEIE : 0; ++ break; ++ + case PCI_EXP_RTSTA: + *value = mvebu_readl(port, PCIE_RC_RTSTA); + break; +@@ -775,6 +808,14 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + break; + + case PCI_INTERRUPT_LINE: ++ if ((mask & (PCI_BRIDGE_CTL_SERR << 16)) && port->error_irq > 0) { ++ u32 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ if (new & (PCI_BRIDGE_CTL_SERR << 16)) ++ unmask |= PCIE_INT_ERR_MASK; ++ else ++ unmask &= ~PCIE_INT_ERR_MASK; ++ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ } + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) +@@ -833,10 +874,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + * PME Status bit in Root Status Register (PCIE_RC_RTSTA) + * is read-only and can be cleared only by writing 0b to the + * Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So +- * clear PME via Interrupt Cause. ++ * clear PME via Interrupt Cause and also set port->pme_pending ++ * variable to false value to start processing PME interrupts ++ * in interrupt handler again. + */ +- if (new & PCI_EXP_RTSTA_PME) ++ if (new & PCI_EXP_RTSTA_PME) { + mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF); ++ port->pme_pending = false; ++ } ++ break; ++ ++ case PCI_EXP_RTCTL: ++ if ((mask & PCI_EXP_RTCTL_PMEIE) && port->error_irq > 0) { ++ u32 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ if (new & PCI_EXP_RTCTL_PMEIE) ++ unmask |= PCIE_INT_PM_PME; ++ else ++ unmask &= ~PCIE_INT_PM_PME; ++ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ } + break; + + case PCI_EXP_DEVCTL2: +@@ -919,6 +975,14 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + bridge_flags |= PCI_BRIDGE_EMUL_NO_IO_FORWARD; + } + ++ /* ++ * Interrupts on emulated bridge are supported only when "error" ++ * interrupt was specified in DT. Without it emulated bridge cannot ++ * emulate interrupts. ++ */ ++ if (port->error_irq > 0) ++ bridge->conf.intpin = PCI_INTERRUPT_INTA; ++ + /* + * Older mvebu hardware provides PCIe Capability structure only in + * version 1. New hardware provides it in version 2. +@@ -1065,6 +1129,26 @@ static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + }; + ++static struct irq_chip rp_irq_chip = { ++ .name = "mvebu-rp", ++}; ++ ++static int mvebu_pcie_rp_irq_map(struct irq_domain *h, ++ unsigned int virq, irq_hw_number_t hwirq) ++{ ++ struct mvebu_pcie_port *port = h->host_data; ++ ++ irq_set_chip_and_handler(virq, &rp_irq_chip, handle_simple_irq); ++ irq_set_chip_data(virq, port); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops mvebu_pcie_rp_irq_domain_ops = { ++ .map = mvebu_pcie_rp_irq_map, ++ .xlate = irq_domain_xlate_onecell, ++}; ++ + static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) + { + struct device *dev = &port->pcie->pdev->dev; +@@ -1087,10 +1171,72 @@ static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) + return -ENOMEM; + } + ++ /* ++ * When "error" interrupt was not specified in DT then there is no ++ * support for interrupts on emulated root bridge. So skip following ++ * initialization. ++ */ ++ if (port->error_irq <= 0) ++ return 0; ++ ++ port->rp_irq_domain = irq_domain_add_linear(NULL, 1, ++ &mvebu_pcie_rp_irq_domain_ops, ++ port); ++ if (!port->rp_irq_domain) { ++ irq_domain_remove(port->intx_irq_domain); ++ dev_err(dev, "Failed to add Root Port IRQ domain for %s\n", port->name); ++ return -ENOMEM; ++ } ++ + return 0; + } + +-static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg) ++static irqreturn_t mvebu_pcie_error_irq_handler(int irq, void *arg) ++{ ++ struct mvebu_pcie_port *port = arg; ++ struct device *dev = &port->pcie->pdev->dev; ++ u32 cause, unmask, status; ++ ++ cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF); ++ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ status = cause & unmask; ++ ++ /* "error" interrupt handler does not process INTX interrupts */ ++ status &= ~(PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | ++ PCIE_INT_INTX(2) | PCIE_INT_INTX(3)); ++ ++ /* Process PME interrupt */ ++ if ((status & PCIE_INT_PM_PME) && !port->pme_pending) { ++ /* ++ * Do not clear PME interrupt bit in Cause Register as it ++ * invalidates also content of Root Status Register. Instead ++ * set port->pme_pending variable to true to indicate that ++ * next time PME interrupt should be ignored until variable ++ * is back to the false value. ++ */ ++ port->pme_pending = true; ++ if (generic_handle_domain_irq(port->rp_irq_domain, 0) == -EINVAL) ++ dev_err_ratelimited(dev, "unhandled PME IRQ\n"); ++ } ++ ++ /* Process ERR interrupt */ ++ if (status & PCIE_INT_ERR_MASK) { ++ mvebu_writel(port, ~PCIE_INT_ERR_MASK, PCIE_INT_CAUSE_OFF); ++ if (generic_handle_domain_irq(port->rp_irq_domain, 0) == -EINVAL) ++ dev_err_ratelimited(dev, "unhandled ERR IRQ\n"); ++ } ++ ++ /* Process local ERR interrupt */ ++ if (status & PCIE_INT_DET_MASK) { ++ mvebu_writel(port, ~PCIE_INT_DET_MASK, PCIE_INT_CAUSE_OFF); ++ if (generic_handle_domain_irq(port->rp_irq_domain, 0) == -EINVAL) ++ dev_err_ratelimited(dev, "unhandled ERR IRQ\n"); ++ } ++ ++ return status ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static irqreturn_t mvebu_pcie_intx_irq_handler(int irq, void *arg) + { + struct mvebu_pcie_port *port = arg; + struct device *dev = &port->pcie->pdev->dev; +@@ -1101,6 +1247,10 @@ static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg) + unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); + status = cause & unmask; + ++ /* "intx" interrupt handler process only INTX interrupts */ ++ status &= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | ++ PCIE_INT_INTX(2) | PCIE_INT_INTX(3); ++ + /* Process legacy INTx interrupts */ + for (i = 0; i < PCI_NUM_INTX; i++) { + if (!(status & PCIE_INT_INTX(i))) +@@ -1115,9 +1265,29 @@ static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg) + + static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { +- /* Interrupt support on mvebu emulated bridges is not implemented yet */ +- if (dev->bus->number == 0) +- return 0; /* Proper return code 0 == NO_IRQ */ ++ struct mvebu_pcie_port *port; ++ struct mvebu_pcie *pcie; ++ ++ if (dev->bus->number == 0) { ++ /* ++ * Each emulated root bridge for every mvebu port has its own ++ * Root Port irq chip and irq domain. Argument pin is the INTx ++ * pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and hwirq for function ++ * irq_create_mapping() is indexed from zero. ++ */ ++ pcie = dev->bus->sysdata; ++ port = mvebu_pcie_find_port(pcie, dev->bus, PCI_DEVFN(slot, 0)); ++ if (!port) ++ return 0; /* Proper return code 0 == NO_IRQ */ ++ /* ++ * port->rp_irq_domain is available only when "error" interrupt ++ * was specified in DT. When is not available then interrupts ++ * for emulated root bridge are not provided. ++ */ ++ if (port->error_irq <= 0) ++ return 0; /* Proper return code 0 == NO_IRQ */ ++ return irq_create_mapping(port->rp_irq_domain, pin - 1); ++ } + + return of_irq_parse_and_map_pci(dev, slot, pin); + } +@@ -1324,6 +1494,21 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, + port->name, child); + } + ++ /* ++ * Old DT bindings do not contain "error" interrupt ++ * so do not fail probing driver when interrupt does not exist. ++ */ ++ port->error_irq = of_irq_get_byname(child, "error"); ++ if (port->error_irq == -EPROBE_DEFER) { ++ ret = port->error_irq; ++ goto err; ++ } ++ if (port->error_irq <= 0) { ++ dev_warn(dev, "%s: interrupts on Root Port are unsupported, " ++ "%pOF does not contain error interrupt\n", ++ port->name, child); ++ } ++ + reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); + if (reset_gpio == -EPROBE_DEFER) { + ret = reset_gpio; +@@ -1529,7 +1714,6 @@ static int mvebu_pcie_probe(struct platform_device *pdev) + + for (i = 0; i < pcie->nports; i++) { + struct mvebu_pcie_port *port = &pcie->ports[i]; +- int irq = port->intx_irq; + + child = port->dn; + if (!child) +@@ -1557,7 +1741,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) + continue; + } + +- if (irq > 0) { ++ if (port->error_irq > 0 || port->intx_irq > 0) { + ret = mvebu_pcie_init_irq_domain(port); + if (ret) { + dev_err(dev, "%s: cannot init irq domain\n", +@@ -1568,14 +1752,42 @@ static int mvebu_pcie_probe(struct platform_device *pdev) + mvebu_pcie_powerdown(port); + continue; + } ++ } ++ ++ if (port->error_irq > 0) { ++ ret = devm_request_irq(dev, port->error_irq, ++ mvebu_pcie_error_irq_handler, ++ IRQF_SHARED | IRQF_NO_THREAD, ++ port->name, port); ++ if (ret) { ++ dev_err(dev, "%s: cannot register error interrupt handler: %d\n", ++ port->name, ret); ++ if (port->intx_irq_domain) ++ irq_domain_remove(port->intx_irq_domain); ++ if (port->rp_irq_domain) ++ irq_domain_remove(port->rp_irq_domain); ++ pci_bridge_emul_cleanup(&port->bridge); ++ devm_iounmap(dev, port->base); ++ port->base = NULL; ++ mvebu_pcie_powerdown(port); ++ continue; ++ } ++ } + +- ret = devm_request_irq(dev, irq, mvebu_pcie_irq_handler, ++ if (port->intx_irq > 0) { ++ ret = devm_request_irq(dev, port->intx_irq, ++ mvebu_pcie_intx_irq_handler, + IRQF_SHARED | IRQF_NO_THREAD, + port->name, port); + if (ret) { +- dev_err(dev, "%s: cannot register interrupt handler: %d\n", ++ dev_err(dev, "%s: cannot register intx interrupt handler: %d\n", + port->name, ret); +- irq_domain_remove(port->intx_irq_domain); ++ if (port->error_irq > 0) ++ devm_free_irq(dev, port->error_irq, port); ++ if (port->intx_irq_domain) ++ irq_domain_remove(port->intx_irq_domain); ++ if (port->rp_irq_domain) ++ irq_domain_remove(port->rp_irq_domain); + pci_bridge_emul_cleanup(&port->bridge); + devm_iounmap(dev, port->base); + port->base = NULL; +@@ -1713,6 +1925,12 @@ static int mvebu_pcie_remove(struct platform_device *pdev) + } + irq_domain_remove(port->intx_irq_domain); + } ++ if (port->rp_irq_domain) { ++ int virq = irq_find_mapping(port->rp_irq_domain, 0); ++ if (virq > 0) ++ irq_dispose_mapping(virq); ++ irq_domain_remove(port->rp_irq_domain); ++ } + + /* Free config space for emulated root bridge. */ + pci_bridge_emul_cleanup(&port->bridge); +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0027-ARM-dts-kirkwood-Add-definitions-for-PCIe-error-inte.patch b/nixos/modules/omnia-kernel-patches/0027-ARM-dts-kirkwood-Add-definitions-for-PCIe-error-inte.patch new file mode 100644 index 0000000..5d907a2 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0027-ARM-dts-kirkwood-Add-definitions-for-PCIe-error-inte.patch @@ -0,0 +1,94 @@ +From 243f3b78a3a2ed0edfc41135abd1f6a047ab684e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:15:56 +0200 +Subject: [PATCH 27/53] ARM: dts: kirkwood: Add definitions for PCIe error + interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +First PCIe controller on Kirkwood SoC reports error interrupt via IRQ 44 +and second PCIe controller via IRQ 45. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/kirkwood-6192.dtsi | 4 ++-- + arch/arm/boot/dts/kirkwood-6281.dtsi | 4 ++-- + arch/arm/boot/dts/kirkwood-6282.dtsi | 8 ++++---- + arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 4 ++-- + 4 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi +index 07f4f7f98c0c..705c0d7effed 100644 +--- a/arch/arm/boot/dts/kirkwood-6192.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6192.dtsi +@@ -26,8 +26,8 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-names = "intx"; +- interrupts = <9>; ++ interrupt-names = "intx", "error"; ++ interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, +diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi +index d08a9a5ecc26..8e311165fd13 100644 +--- a/arch/arm/boot/dts/kirkwood-6281.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6281.dtsi +@@ -26,8 +26,8 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-names = "intx"; +- interrupts = <9>; ++ interrupt-names = "intx", "error"; ++ interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, +diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi +index 2eea5b304f47..e33723160ce7 100644 +--- a/arch/arm/boot/dts/kirkwood-6282.dtsi ++++ b/arch/arm/boot/dts/kirkwood-6282.dtsi +@@ -30,8 +30,8 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-names = "intx"; +- interrupts = <9>; ++ interrupt-names = "intx", "error"; ++ interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, +@@ -58,8 +58,8 @@ pcie1: pcie@2,0 { + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-names = "intx"; +- interrupts = <10>; ++ interrupt-names = "intx", "error"; ++ interrupts = <10>, <45>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, +diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +index 070bc13242b8..c3469a2fc58a 100644 +--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi ++++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +@@ -26,8 +26,8 @@ pcie0: pcie@1,0 { + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-names = "intx"; +- interrupts = <9>; ++ interrupt-names = "intx", "error"; ++ interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0028-ARM-dts-dove-Add-definitions-for-PCIe-error-interrup.patch b/nixos/modules/omnia-kernel-patches/0028-ARM-dts-dove-Add-definitions-for-PCIe-error-interrup.patch new file mode 100644 index 0000000..f5d3d01 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0028-ARM-dts-dove-Add-definitions-for-PCIe-error-interrup.patch @@ -0,0 +1,46 @@ +From dde5cc0a6f29751b2221f05529cadeff3f7d38af Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:18:11 +0200 +Subject: [PATCH 28/53] ARM: dts: dove: Add definitions for PCIe error + interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +First PCIe controller on Dove SoC reports error interrupt via IRQ 15 +and second PCIe controller via IRQ 17. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/dove.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi +index 70d45d2b1258..9aee3cfd3e98 100644 +--- a/arch/arm/boot/dts/dove.dtsi ++++ b/arch/arm/boot/dts/dove.dtsi +@@ -122,8 +122,8 @@ pcie0: pcie@1 { + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; +- interrupt-names = "intx"; +- interrupts = <16>; ++ interrupt-names = "intx", "error"; ++ interrupts = <16>, <15>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, +@@ -151,8 +151,8 @@ pcie1: pcie@2 { + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; +- interrupt-names = "intx"; +- interrupts = <18>; ++ interrupt-names = "intx", "error"; ++ interrupts = <18>, <17>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch b/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch new file mode 100644 index 0000000..29bb342 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch @@ -0,0 +1,42 @@ +From 74acdb46ee1c31a4071bc25deaa6a9ed6e10229e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 6 May 2022 14:22:28 +0200 +Subject: [PATCH 29/53] dt-bindings: irqchip: armada-370-xp: Update information + about MPIC SoC Error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + .../interrupt-controller/marvell,armada-370-xp-mpic.txt | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +index 5fc03134a999..8cddbc16ddbd 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt ++++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +@@ -24,6 +24,11 @@ Optional properties: + connected as a slave to the Cortex-A9 GIC. The provided interrupt + indicate to which GIC interrupt the MPIC output is connected. + ++Optional subnodes: ++ ++- interrupt-controller@20 with interrupt-controller property for ++ MPIC SoC Error IRQ controller ++ + Example: + + mpic: interrupt-controller@d0020000 { +@@ -35,4 +40,8 @@ Example: + msi-controller; + reg = <0xd0020a00 0x1d0>, + <0xd0021070 0x58>; ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0030-ARM-dts-armada-370-xp.dtsi-Add-node-for-MPIC-SoC-Err.patch b/nixos/modules/omnia-kernel-patches/0030-ARM-dts-armada-370-xp.dtsi-Add-node-for-MPIC-SoC-Err.patch new file mode 100644 index 0000000..41e8188 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0030-ARM-dts-armada-370-xp.dtsi-Add-node-for-MPIC-SoC-Err.patch @@ -0,0 +1,33 @@ +From f2fcf2b0fd2bfb2be5c84e0ad361c91199fd483a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:25:39 +0200 +Subject: [PATCH 30/53] ARM: dts: armada-370-xp.dtsi: Add node for MPIC SoC + Error IRQ controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi +index 0b8c2a64b36f..7aedacff2c00 100644 +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -171,6 +171,11 @@ mpic: interrupt-controller@20a00 { + #size-cells = <1>; + interrupt-controller; + msi-controller; ++ ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + coherencyfab: coherency-fabric@20200 { +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0031-ARM-dts-armada-375.dtsi-Add-node-for-MPIC-SoC-Error-.patch b/nixos/modules/omnia-kernel-patches/0031-ARM-dts-armada-375.dtsi-Add-node-for-MPIC-SoC-Error-.patch new file mode 100644 index 0000000..cc5a13c --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0031-ARM-dts-armada-375.dtsi-Add-node-for-MPIC-SoC-Error-.patch @@ -0,0 +1,33 @@ +From 25e82e6c0c3cc72bdb81e299b0609717cb4dba1a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:43:14 +0200 +Subject: [PATCH 31/53] ARM: dts: armada-375.dtsi: Add node for MPIC SoC Error + IRQ controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-375.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi +index c310ef26d1cc..82f0a59d112f 100644 +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -376,6 +376,11 @@ mpic: interrupt-controller@20a00 { + interrupt-controller; + msi-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; ++ ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + timer1: timer@20300 { +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0032-ARM-dts-armada-38x.dtsi-Add-node-for-MPIC-SoC-Error-.patch b/nixos/modules/omnia-kernel-patches/0032-ARM-dts-armada-38x.dtsi-Add-node-for-MPIC-SoC-Error-.patch new file mode 100644 index 0000000..a10e952 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0032-ARM-dts-armada-38x.dtsi-Add-node-for-MPIC-SoC-Error-.patch @@ -0,0 +1,35 @@ +From 93d56001ec0e1b4c1d345fb5c59685aa43d76091 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 18 Apr 2022 00:39:52 +0200 +Subject: [PATCH 32/53] ARM: dts: armada-38x.dtsi: Add node for MPIC SoC Error + IRQ controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It is child of the MPIC IRQ controller. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi +index df3c8d1d8f64..099f167b65aa 100644 +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -398,6 +398,11 @@ mpic: interrupt-controller@20a00 { + interrupt-controller; + msi-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; ++ ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + timer: timer@20300 { +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0033-ARM-dts-armada-39x.dtsi-Add-node-for-MPIC-SoC-Error-.patch b/nixos/modules/omnia-kernel-patches/0033-ARM-dts-armada-39x.dtsi-Add-node-for-MPIC-SoC-Error-.patch new file mode 100644 index 0000000..95fc415 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0033-ARM-dts-armada-39x.dtsi-Add-node-for-MPIC-SoC-Error-.patch @@ -0,0 +1,33 @@ +From 41c757f4171acee0380527a78fb335a617076c4c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:49:36 +0200 +Subject: [PATCH 33/53] ARM: dts: armada-39x.dtsi: Add node for MPIC SoC Error + IRQ controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-39x.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi +index 9d1cac49c022..f21231a1f244 100644 +--- a/arch/arm/boot/dts/armada-39x.dtsi ++++ b/arch/arm/boot/dts/armada-39x.dtsi +@@ -272,6 +272,11 @@ mpic: interrupt-controller@20a00 { + interrupt-controller; + msi-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; ++ ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + timer@20300 { +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0034-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-err.patch b/nixos/modules/omnia-kernel-patches/0034-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-err.patch new file mode 100644 index 0000000..affb1ef --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0034-ARM-dts-armada-370.dtsi-Add-definitions-for-PCIe-err.patch @@ -0,0 +1,43 @@ +From 764a103390fccf4c2ba404315124a3a96982f049 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:31:57 +0200 +Subject: [PATCH 34/53] ARM: dts: armada-370.dtsi: Add definitions for PCIe + error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-370.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi +index 2013a5ccecd3..9daece786a53 100644 +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -60,8 +60,8 @@ pcie0: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 58>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 58>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -88,8 +88,8 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 62>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 62>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0035-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0035-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..f3bdb07 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0035-ARM-dts-armada-xp-mv78230.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,79 @@ +From 788daf7d92efbe1219ccb3a299f38894ff10f2f0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 19:33:45 +0200 +Subject: [PATCH 35/53] ARM: dts: armada-xp-mv78230.dtsi: Add definitions for + PCIe error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PCIe controllers on Marvell Port 0 share MPIC SoC Error IRQ 4 and PCIe +controller on Marvell Port 1 uses MPIC SoC Error IRQ 5. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +index 5ea9d509cd30..b8d169c4feec 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -83,8 +83,8 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 58>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 58>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -111,8 +111,8 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 59>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 59>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -139,8 +139,8 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 60>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 60>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +@@ -167,8 +167,8 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 61>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 61>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; +@@ -195,8 +195,8 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 62>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 62>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0036-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0036-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..bc8b743 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0036-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,124 @@ +From b70eb040e50bfa7787d5630ce00687e225604393 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:02:26 +0200 +Subject: [PATCH 36/53] ARM: dts: armada-xp-mv78260.dtsi: Add definitions for + PCIe error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PCIe controllers on Marvell Port 0 share MPIC SoC Error IRQ 4, PCIe +controllers on Marvell Port 1 share MPIC SoC Error IRQ 5 and PCIe +controller on Marvell Port 2 uses MPIC SoC Error IRQ 15. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 36 ++++++++++++------------ + 1 file changed, 18 insertions(+), 18 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +index 6c6fbb9faf5a..febd9d98a44e 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -98,8 +98,8 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 58>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 58>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -126,8 +126,8 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 59>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 59>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -154,8 +154,8 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 60>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 60>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +@@ -182,8 +182,8 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 61>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 61>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; +@@ -210,8 +210,8 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 62>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 62>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; +@@ -238,8 +238,8 @@ pcie6: pcie@6,0 { + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 63>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 63>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; +@@ -266,8 +266,8 @@ pcie7: pcie@7,0 { + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 64>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 64>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; +@@ -294,8 +294,8 @@ pcie8: pcie@8,0 { + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 65>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 65>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; +@@ -322,8 +322,8 @@ pcie9: pcie@9,0 { + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 99>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 99>, <&soc_err 15>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0037-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0037-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch new file mode 100644 index 0000000..a0c25e8 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0037-ARM-dts-armada-xp-mv78460.dtsi-Add-definitions-for-P.patch @@ -0,0 +1,136 @@ +From 8fd6810b2e79de165b63efcd1be248cc4420447d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 20:05:35 +0200 +Subject: [PATCH 37/53] ARM: dts: armada-xp-mv78460.dtsi: Add definitions for + PCIe error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PCIe controllers on Marvell Port 0 share MPIC SoC Error IRQ 4, PCIe +controllers on Marvell Port 1 share MPIC SoC Error IRQ 5, PCIe +controller on Marvell Port 2 uses MPIC SoC Error IRQ 15 and PCIe +controller on Marvell Port 3 uses MPIC SoC Error IRQ 16. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 40 ++++++++++++------------ + 1 file changed, 20 insertions(+), 20 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +index 16185edf9aa5..3b8adbc89a06 100644 +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -119,8 +119,8 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 58>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 58>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -147,8 +147,8 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 59>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 59>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -175,8 +175,8 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 60>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 60>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +@@ -203,8 +203,8 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 61>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 61>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; +@@ -231,8 +231,8 @@ pcie5: pcie@5,0 { + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 62>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 62>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; +@@ -259,8 +259,8 @@ pcie6: pcie@6,0 { + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 63>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 63>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; +@@ -287,8 +287,8 @@ pcie7: pcie@7,0 { + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 64>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 64>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; +@@ -315,8 +315,8 @@ pcie8: pcie@8,0 { + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 65>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 65>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; +@@ -343,8 +343,8 @@ pcie9: pcie@9,0 { + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 99>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 99>, <&soc_err 15>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; +@@ -371,8 +371,8 @@ pcie10: pcie@a,0 { + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 103>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 103>, <&soc_err 16>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0038-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch b/nixos/modules/omnia-kernel-patches/0038-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch new file mode 100644 index 0000000..4832b21 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0038-ARM-dts-armada-xp-98dx3236.dtsi-Add-definitions-for-.patch @@ -0,0 +1,32 @@ +From 6c135c7f53257d155b6e3e5279d55544b095346a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:30:55 +0200 +Subject: [PATCH 38/53] ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for + PCIe error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +index b21ffb819b1d..0d021f3b86be 100644 +--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi ++++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +@@ -76,8 +76,8 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&mpic 58>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&mpic 58>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0039-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-err.patch b/nixos/modules/omnia-kernel-patches/0039-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-err.patch new file mode 100644 index 0000000..5f3d631 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0039-ARM-dts-armada-375.dtsi-Add-definitions-for-PCIe-err.patch @@ -0,0 +1,43 @@ +From dcac6147ecb20f76c53887dd419c6607a461f816 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 16:45:29 +0200 +Subject: [PATCH 39/53] ARM: dts: armada-375.dtsi: Add definitions for PCIe + error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-375.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi +index 82f0a59d112f..71b01a089c81 100644 +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -573,8 +573,8 @@ pcie0: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -601,8 +601,8 @@ pcie1: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0040-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-err.patch b/nixos/modules/omnia-kernel-patches/0040-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-err.patch new file mode 100644 index 0000000..48f0e51 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0040-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-err.patch @@ -0,0 +1,57 @@ +From 70176e0326ce3f7aaacfec2e5165a63c97c5ae9a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:41:39 +0200 +Subject: [PATCH 40/53] ARM: dts: armada-380.dtsi: Add definitions for PCIe + error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-380.dtsi | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi +index e94f22b0e9b5..970ac6820db9 100644 +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -64,8 +64,9 @@ pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -93,8 +94,9 @@ pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -122,8 +124,9 @@ pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 15>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0041-ARM-dts-armada-385.dtsi-Add-definitions-for-PCIe-err.patch b/nixos/modules/omnia-kernel-patches/0041-ARM-dts-armada-385.dtsi-Add-definitions-for-PCIe-err.patch new file mode 100644 index 0000000..9d80899 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0041-ARM-dts-armada-385.dtsi-Add-definitions-for-PCIe-err.patch @@ -0,0 +1,71 @@ +From 40e275d7eba809c9be431eb881c2ef1086747e0b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 18 Apr 2022 00:40:05 +0200 +Subject: [PATCH 41/53] ARM: dts: armada-385.dtsi: Add definitions for PCIe + error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PCIe error interrupt is reported by MPIC SoC Error IRQ controller. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-385.dtsi | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi +index be8d607c59b2..d603de5aa574 100644 +--- a/arch/arm/boot/dts/armada-385.dtsi ++++ b/arch/arm/boot/dts/armada-385.dtsi +@@ -69,8 +69,9 @@ pcie1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -97,8 +98,9 @@ pcie2: pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -125,8 +127,9 @@ pcie3: pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 15>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +@@ -156,8 +159,9 @@ pcie4: pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 16>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0042-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-err.patch b/nixos/modules/omnia-kernel-patches/0042-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-err.patch new file mode 100644 index 0000000..5c22a74 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0042-ARM-dts-armada-39x.dtsi-Add-definitions-for-PCIe-err.patch @@ -0,0 +1,69 @@ +From c0ac4265f9e786f71be01cb34303faaba2b70016 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:50:54 +0200 +Subject: [PATCH 42/53] ARM: dts: armada-39x.dtsi: Add definitions for PCIe + error interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-39x.dtsi | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi +index f21231a1f244..f58bd456e5ad 100644 +--- a/arch/arm/boot/dts/armada-39x.dtsi ++++ b/arch/arm/boot/dts/armada-39x.dtsi +@@ -443,8 +443,9 @@ pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 4>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; +@@ -472,8 +473,9 @@ pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 5>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; +@@ -501,8 +503,9 @@ pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 15>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; +@@ -533,8 +536,9 @@ pcie@4,0 { + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +- interrupt-names = "intx"; +- interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "intx", "error"; ++ interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, ++ <&soc_err 16>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0043-PCI-pciehp-Enable-DLLSC-interrupt-only-if-supported.patch b/nixos/modules/omnia-kernel-patches/0043-PCI-pciehp-Enable-DLLSC-interrupt-only-if-supported.patch new file mode 100644 index 0000000..17b5aea --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0043-PCI-pciehp-Enable-DLLSC-interrupt-only-if-supported.patch @@ -0,0 +1,139 @@ +From 337891ffea7c9e65b456663e080028371401f3be Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 31 Mar 2021 15:12:50 +0200 +Subject: [PATCH 43/53] PCI: pciehp: Enable DLLSC interrupt only if supported +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Don't enable Data Link Layer State Changed interrupt if it isn't +supported. + +Data Link Layer Link Active Reporting Capable bit in Link Capabilities +register indicates if Data Link Layer State Changed Enable is supported. + +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/hotplug/pciehp_hpc.c | 32 ++++++++++++++++++++++++-------- + drivers/pci/hotplug/pnv_php.c | 13 +++++++++---- + 2 files changed, 33 insertions(+), 12 deletions(-) + +diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c +index 040ae076ec0e..ef807c79b1b1 100644 +--- a/drivers/pci/hotplug/pciehp_hpc.c ++++ b/drivers/pci/hotplug/pciehp_hpc.c +@@ -788,6 +788,7 @@ static int pciehp_poll(void *data) + static void pcie_enable_notification(struct controller *ctrl) + { + u16 cmd, mask; ++ u32 link_cap; + + /* + * TBD: Power fault detected software notification support. +@@ -800,12 +801,17 @@ static void pcie_enable_notification(struct controller *ctrl) + * next power fault detected interrupt was notified again. + */ + ++ pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); ++ + /* +- * Always enable link events: thus link-up and link-down shall +- * always be treated as hotplug and unplug respectively. Enable +- * presence detect only if Attention Button is not present. +- */ +- cmd = PCI_EXP_SLTCTL_DLLSCE; ++ * Enable link events if their support is indicated in Link Capability ++ * register: thus link-up and link-down shall always be treated as ++ * hotplug and unplug respectively. Enable presence detect only if ++ * Attention Button is not present. ++ */ ++ cmd = 0; ++ if (link_cap & PCI_EXP_LNKCAP_DLLLARC) ++ cmd |= PCI_EXP_SLTCTL_DLLSCE; + if (ATTN_BUTTN(ctrl)) + cmd |= PCI_EXP_SLTCTL_ABPE; + else +@@ -845,8 +851,13 @@ void pcie_clear_hotplug_events(struct controller *ctrl) + void pcie_enable_interrupt(struct controller *ctrl) + { + u16 mask; ++ u32 link_cap; + +- mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; ++ pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); ++ ++ mask = PCI_EXP_SLTCTL_HPIE; ++ if (link_cap & PCI_EXP_LNKCAP_DLLLARC) ++ mask |= PCI_EXP_SLTCTL_DLLSCE; + pcie_write_cmd(ctrl, mask, mask); + } + +@@ -904,19 +915,24 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) + struct controller *ctrl = to_ctrl(hotplug_slot); + struct pci_dev *pdev = ctrl_dev(ctrl); + u16 stat_mask = 0, ctrl_mask = 0; ++ u32 link_cap; + int rc; + + if (probe) + return 0; + ++ pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); ++ + down_write_nested(&ctrl->reset_lock, ctrl->depth); + + if (!ATTN_BUTTN(ctrl)) { + ctrl_mask |= PCI_EXP_SLTCTL_PDCE; + stat_mask |= PCI_EXP_SLTSTA_PDC; + } +- ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; +- stat_mask |= PCI_EXP_SLTSTA_DLLSC; ++ if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { ++ ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; ++ stat_mask |= PCI_EXP_SLTSTA_DLLSC; ++ } + + pcie_write_cmd(ctrl, 0, ctrl_mask); + ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, +diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c +index 881d420637bf..5c700d3a9009 100644 +--- a/drivers/pci/hotplug/pnv_php.c ++++ b/drivers/pci/hotplug/pnv_php.c +@@ -840,6 +840,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) + { + struct pci_dev *pdev = php_slot->pdev; + u32 broken_pdc = 0; ++ u32 link_cap; + u16 sts, ctrl; + int ret; + +@@ -874,17 +875,21 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) + return; + } + ++ pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); ++ + /* Enable the interrupts */ + pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &ctrl); + if (php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC) { + ctrl &= ~PCI_EXP_SLTCTL_PDCE; +- ctrl |= (PCI_EXP_SLTCTL_HPIE | +- PCI_EXP_SLTCTL_DLLSCE); ++ ctrl |= PCI_EXP_SLTCTL_HPIE; + } else { + ctrl |= (PCI_EXP_SLTCTL_HPIE | +- PCI_EXP_SLTCTL_PDCE | +- PCI_EXP_SLTCTL_DLLSCE); ++ PCI_EXP_SLTCTL_PDCE); + } ++ if (link_cap & PCI_EXP_LNKCAP_DLLLARC) ++ ctrl |= PCI_EXP_SLTCTL_DLLSCE; ++ else ++ ctrl &= ~PCI_EXP_SLTCTL_DLLSCE; + pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl); + + /* The interrupt is initialized successfully when @irq is valid */ +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0044-PCI-pciehp-Enable-Command-Completed-Interrupt-only-i.patch b/nixos/modules/omnia-kernel-patches/0044-PCI-pciehp-Enable-Command-Completed-Interrupt-only-i.patch new file mode 100644 index 0000000..5a658e7 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0044-PCI-pciehp-Enable-Command-Completed-Interrupt-only-i.patch @@ -0,0 +1,38 @@ +From 37248c705254f050fb67b107eb389a378ab0428e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 31 Mar 2021 15:14:29 +0200 +Subject: [PATCH 44/53] PCI: pciehp: Enable Command Completed Interrupt only if + supported +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The No Command Completed Support bit in the Slot Capabilities register +indicates whether Command Completed Interrupt Enable is unsupported. + +Enable this interrupt only in the case it is supported. + +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/hotplug/pciehp_hpc.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c +index ef807c79b1b1..a5199b312e74 100644 +--- a/drivers/pci/hotplug/pciehp_hpc.c ++++ b/drivers/pci/hotplug/pciehp_hpc.c +@@ -817,7 +817,9 @@ static void pcie_enable_notification(struct controller *ctrl) + else + cmd |= PCI_EXP_SLTCTL_PDCE; + if (!pciehp_poll_mode) +- cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; ++ cmd |= PCI_EXP_SLTCTL_HPIE; ++ if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl)) ++ cmd |= PCI_EXP_SLTCTL_CCIE; + + mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | + PCI_EXP_SLTCTL_PFDE | +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0045-PCI-mvebu-Add-support-for-PCI_EXP_SLTSTA_DLLSC-via-h.patch b/nixos/modules/omnia-kernel-patches/0045-PCI-mvebu-Add-support-for-PCI_EXP_SLTSTA_DLLSC-via-h.patch new file mode 100644 index 0000000..128e012 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0045-PCI-mvebu-Add-support-for-PCI_EXP_SLTSTA_DLLSC-via-h.patch @@ -0,0 +1,297 @@ +From 6130515a14b0ef390507edc5b232996a1bcfccbc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 17 Sep 2021 14:53:11 +0200 +Subject: [PATCH 45/53] PCI: mvebu: Add support for PCI_EXP_SLTSTA_DLLSC via + hot plug interrupt +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If link up/down state is changed in mvebu_pcie_link_up() then trigger +hot plug interrupt with DLLSC state change. + +Also triggers hot plug interrupt when mvebu triggers Link Failure interrupt +which indicates that link was changed from active state or when mvebu +triggers TxReq No Link interrupt which indicates that link is down while +trying to transmit PCIe transaction. + +And this hot plug interrupt also when explicit Link Disable or PCIe Host +Reset is issued as mvebu does not trigger Link Failure when dropping to +Detect via Hot Reset or Link Disable. + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/Kconfig | 3 + + drivers/pci/controller/pci-mvebu.c | 147 ++++++++++++++++++++++++++++- + 2 files changed, 149 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index d1c5fcf00a8a..8da2efdc5177 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -10,6 +10,9 @@ config PCI_MVEBU + depends on ARM + depends on OF + select PCI_BRIDGE_EMUL ++ select PCIEPORTBUS ++ select HOTPLUG_PCI ++ select HOTPLUG_PCI_PCIE + help + Add support for Marvell EBU PCIe controller. This PCIe controller + is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370, +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index ddd5ba8b265e..634ca84cfda2 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -56,12 +56,14 @@ + #define PCIE_CONF_DATA_OFF 0x18fc + #define PCIE_INT_CAUSE_OFF 0x1900 + #define PCIE_INT_UNMASK_OFF 0x1910 ++#define PCIE_INT_TXREQ_NOLINK BIT(0) + #define PCIE_INT_DET_COR BIT(8) + #define PCIE_INT_DET_NONFATAL BIT(9) + #define PCIE_INT_DET_FATAL BIT(10) + #define PCIE_INT_ERR_FATAL BIT(16) + #define PCIE_INT_ERR_NONFATAL BIT(17) + #define PCIE_INT_ERR_COR BIT(18) ++#define PCIE_INT_LINK_FAIL BIT(23) + #define PCIE_INT_INTX(i) BIT(24+i) + #define PCIE_INT_PM_PME BIT(28) + #define PCIE_INT_DET_MASK (PCIE_INT_DET_COR | PCIE_INT_DET_NONFATAL | PCIE_INT_DET_FATAL) +@@ -134,6 +136,8 @@ struct mvebu_pcie_port { + int error_irq; + int intx_irq; + bool pme_pending; ++ struct timer_list link_irq_timer; ++ bool link_was_up; + }; + + static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) +@@ -153,7 +157,26 @@ static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) + + static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) + { +- return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); ++ bool link_is_up; ++ u16 slotsta; ++ ++ link_is_up = !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); ++ ++ if (link_is_up != port->link_was_up) { ++ port->link_was_up = link_is_up; ++ /* ++ * Link IRQ timer/handler is available only when "error" ++ * interrupt was specified in DT. ++ */ ++ if (port->error_irq > 0) { ++ slotsta = le16_to_cpu(port->bridge.pcie_conf.slotsta); ++ port->bridge.pcie_conf.slotsta = ++ cpu_to_le16(slotsta | PCI_EXP_SLTSTA_DLLSC); ++ mod_timer(&port->link_irq_timer, jiffies + 1); ++ } ++ } ++ ++ return link_is_up; + } + + static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port) +@@ -346,6 +369,19 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); + } + ++ /* ++ * Unmask No Link and Link Failure interrupts to process Link Down ++ * events. These events are reported as Data Link Layer State Changed ++ * notification via Hot Plug Interrupt. Other parts of Link change ++ * events are available only when "error" interrupt was specified in DT. ++ * So enable these interrupts under same conditions. ++ */ ++ if (port->error_irq > 0) { ++ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ unmask |= PCIE_INT_TXREQ_NOLINK | PCIE_INT_LINK_FAIL; ++ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); ++ } ++ + /* + * Fallback code when "intx" interrupt was not specified in DT: + * Unmask all legacy INTx interrupts as driver does not provide a way +@@ -692,6 +728,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE; + else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE)) + val |= PCI_EXP_SLTCTL_ASPL_DISABLE; ++ /* ++ * HPIE and DLLSCE bits are stored only in emulated config ++ * space buffer and are supported only when or "error" interrupt ++ * was specified in DT. ++ */ ++ if (port->error_irq > 0) ++ val |= slotctl & (PCI_EXP_SLTCTL_HPIE | ++ PCI_EXP_SLTCTL_DLLSCE); + /* This callback is 32-bit and in high bits is slot status. */ + val |= slotsta << 16; + *value = val; +@@ -823,6 +867,25 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + else + ctrl &= ~PCIE_CTRL_MASTER_HOT_RESET; + mvebu_writel(port, ctrl, PCIE_CTRL_OFF); ++ /* ++ * When dropping to Detect via Hot Reset, Disable Link ++ * or Loopback states, the Link Failure interrupt is not ++ * asserted. So when setting Secondary Bus Reset / Hot ++ * Reset bit, call link IRQ timer/handler manually. ++ */ ++ if ((ctrl & PCIE_CTRL_MASTER_HOT_RESET) && port->link_was_up) { ++ port->link_was_up = false; ++ /* ++ * Link IRQ timer/handler is available only when ++ * "error" interrupt was specified in DT. ++ */ ++ if (port->error_irq > 0) { ++ u16 slotsta = le16_to_cpu(port->bridge.pcie_conf.slotsta); ++ port->bridge.pcie_conf.slotsta = ++ cpu_to_le16(slotsta | PCI_EXP_SLTSTA_DLLSC); ++ mod_timer(&port->link_irq_timer, jiffies + 1); ++ } ++ } + } + break; + +@@ -851,6 +914,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; + + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); ++ /* ++ * When dropping to Detect via Hot Reset, Disable Link ++ * or Loopback states, the Link Failure interrupt is not ++ * asserted. So when setting Link Disable bit, call link ++ * IRQ timer/handler manually. ++ */ ++ if ((new & PCI_EXP_LNKCTL_LD) && port->link_was_up) { ++ port->link_was_up = false; ++ /* ++ * Link IRQ timer/handler is available only when ++ * "error" interrupt was specified in DT. ++ */ ++ if (port->error_irq > 0) { ++ u16 slotsta = le16_to_cpu(port->bridge.pcie_conf.slotsta); ++ port->bridge.pcie_conf.slotsta = ++ cpu_to_le16(slotsta | PCI_EXP_SLTSTA_DLLSC); ++ mod_timer(&port->link_irq_timer, jiffies + 1); ++ } ++ } + break; + + case PCI_EXP_SLTCTL: +@@ -991,6 +1073,15 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver | PCI_EXP_FLAGS_SLOT); + + /* ++ * When "error" interrupt was specified in DT then driver is able to ++ * deliver Data Link Layer State Change interrupt. So in this case mark ++ * bridge as Hot Plug Capable as this is the way how to enable ++ * delivering of Data Link Layer State Change interrupts. ++ * ++ * No Command Completed Support is set because bridge does not support ++ * Command Completed Interrupt. Every command is executed immediately ++ * without any delay. ++ * + * Set Presence Detect State bit permanently as there is no support for + * unplugging PCIe card from the slot. Assume that PCIe card is always + * connected in slot. +@@ -1002,6 +1093,8 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + * Also set correct slot power limit. + */ + bridge->pcie_conf.slotcap = cpu_to_le32( ++ PCI_EXP_SLTCAP_NCCS | ++ (port->error_irq > 0 ? PCI_EXP_SLTCAP_HPC : 0) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) | + FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1)); +@@ -1191,11 +1284,29 @@ static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) + return 0; + } + ++static void mvebu_pcie_link_irq_handler(struct timer_list *timer) ++{ ++ struct mvebu_pcie_port *port = from_timer(port, timer, link_irq_timer); ++ struct device *dev = &port->pcie->pdev->dev; ++ u16 slotctl; ++ ++ dev_info(dev, "%s: link %s\n", port->name, port->link_was_up ? "up" : "down"); ++ ++ slotctl = le16_to_cpu(port->bridge.pcie_conf.slotctl); ++ if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || ++ !(slotctl & PCI_EXP_SLTCTL_HPIE)) ++ return; ++ ++ if (generic_handle_domain_irq(port->rp_irq_domain, 0) == -EINVAL) ++ dev_err_ratelimited(dev, "unhandled HP IRQ\n"); ++} ++ + static irqreturn_t mvebu_pcie_error_irq_handler(int irq, void *arg) + { + struct mvebu_pcie_port *port = arg; + struct device *dev = &port->pcie->pdev->dev; + u32 cause, unmask, status; ++ u16 slotsta; + + cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF); + unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); +@@ -1233,6 +1344,25 @@ static irqreturn_t mvebu_pcie_error_irq_handler(int irq, void *arg) + dev_err_ratelimited(dev, "unhandled ERR IRQ\n"); + } + ++ /* Process No Link and Link Failure interrupts as HP IRQ */ ++ if (status & (PCIE_INT_TXREQ_NOLINK | PCIE_INT_LINK_FAIL)) { ++ mvebu_writel(port, ++ ~(PCIE_INT_TXREQ_NOLINK | PCIE_INT_LINK_FAIL), ++ PCIE_INT_CAUSE_OFF); ++ if (port->link_was_up) { ++ port->link_was_up = false; ++ slotsta = le16_to_cpu(port->bridge.pcie_conf.slotsta); ++ port->bridge.pcie_conf.slotsta = ++ cpu_to_le16(slotsta | PCI_EXP_SLTSTA_DLLSC); ++ /* ++ * Deactivate timer and call mvebu_pcie_link_irq_handler() ++ * function directly as we are in the interrupt context. ++ */ ++ del_timer_sync(&port->link_irq_timer); ++ mvebu_pcie_link_irq_handler(&port->link_irq_timer); ++ } ++ } ++ + return status ? IRQ_HANDLED : IRQ_NONE; + } + +@@ -1796,6 +1926,18 @@ static int mvebu_pcie_probe(struct platform_device *pdev) + } + } + ++ /* ++ * Function mvebu_pcie_link_irq_handler() calls function ++ * generic_handle_irq() and it expects local IRQs to be disabled ++ * as normally generic_handle_irq() is called from the interrupt ++ * context. So use TIMER_IRQSAFE flag for this link_irq_timer. ++ * Available only if "or "error" interrupt was specified. ++ */ ++ if (port->error_irq > 0) ++ timer_setup(&port->link_irq_timer, ++ mvebu_pcie_link_irq_handler, ++ TIMER_IRQSAFE); ++ + /* + * PCIe topology exported by mvebu hw is quite complicated. In + * reality has something like N fully independent host bridges +@@ -1932,6 +2074,9 @@ static int mvebu_pcie_remove(struct platform_device *pdev) + irq_domain_remove(port->rp_irq_domain); + } + ++ if (port->error_irq > 0) ++ del_timer_sync(&port->link_irq_timer); ++ + /* Free config space for emulated root bridge. */ + pci_bridge_emul_cleanup(&port->bridge); + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0046-PCI-mvebu-use-BIT-and-GENMASK-macros-instead-of-hard.patch b/nixos/modules/omnia-kernel-patches/0046-PCI-mvebu-use-BIT-and-GENMASK-macros-instead-of-hard.patch new file mode 100644 index 0000000..8ecc769 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0046-PCI-mvebu-use-BIT-and-GENMASK-macros-instead-of-hard.patch @@ -0,0 +1,47 @@ +From f893f9d475f7124c4bf104ac42e6e449f8fb6e2c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 17 Sep 2021 14:54:29 +0200 +Subject: [PATCH 46/53] PCI: mvebu: use BIT() and GENMASK() macros instead of + hardcoded hex values +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 634ca84cfda2..4e4b4da89ac7 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -44,7 +44,7 @@ + #define PCIE_WIN5_BASE_OFF 0x1884 + #define PCIE_WIN5_REMAP_OFF 0x188c + #define PCIE_CONF_ADDR_OFF 0x18f8 +-#define PCIE_CONF_ADDR_EN 0x80000000 ++#define PCIE_CONF_ADDR_EN BIT(31) + #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) + #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) + #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +@@ -70,13 +70,13 @@ + #define PCIE_INT_ERR_MASK (PCIE_INT_ERR_FATAL | PCIE_INT_ERR_NONFATAL | PCIE_INT_ERR_COR) + #define PCIE_INT_ALL_MASK GENMASK(31, 0) + #define PCIE_CTRL_OFF 0x1a00 +-#define PCIE_CTRL_X1_MODE 0x0001 ++#define PCIE_CTRL_X1_MODE BIT(0) + #define PCIE_CTRL_RC_MODE BIT(1) + #define PCIE_CTRL_MASTER_HOT_RESET BIT(24) + #define PCIE_STAT_OFF 0x1a04 +-#define PCIE_STAT_BUS 0xff00 +-#define PCIE_STAT_DEV 0x1f0000 + #define PCIE_STAT_LINK_DOWN BIT(0) ++#define PCIE_STAT_BUS GENMASK(15, 8) ++#define PCIE_STAT_DEV GENMASK(20, 16) + #define PCIE_SSPL_OFF 0x1a0c + #define PCIE_SSPL_VALUE_SHIFT 0 + #define PCIE_SSPL_VALUE_MASK GENMASK(7, 0) +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0047-PCI-mvebu-For-consistency-add-_OFF-suffix-to-all-reg.patch b/nixos/modules/omnia-kernel-patches/0047-PCI-mvebu-For-consistency-add-_OFF-suffix-to-all-reg.patch new file mode 100644 index 0000000..43d70de --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0047-PCI-mvebu-For-consistency-add-_OFF-suffix-to-all-reg.patch @@ -0,0 +1,167 @@ +From c5a1551bec43424642c5400df6bc07966a6de891 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Fri, 17 Sep 2021 14:55:03 +0200 +Subject: [PATCH 47/53] PCI: mvebu: For consistency add _OFF suffix to all + registers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-mvebu.c | 40 +++++++++++++++--------------- + 1 file changed, 20 insertions(+), 20 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 4e4b4da89ac7..e36dbf4ccd79 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -34,7 +34,7 @@ + #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) + #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) + #define PCIE_SSDEV_ID_OFF 0x002c +-#define PCIE_CAP_PCIEXP 0x0060 ++#define PCIE_CAP_PCIEXP_OFF 0x0060 + #define PCIE_CAP_PCIERR_OFF 0x0100 + #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) + #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) +@@ -83,8 +83,8 @@ + #define PCIE_SSPL_SCALE_SHIFT 8 + #define PCIE_SSPL_SCALE_MASK GENMASK(9, 8) + #define PCIE_SSPL_ENABLE BIT(16) +-#define PCIE_RC_RTSTA 0x1a14 +-#define PCIE_DEBUG_CTRL 0x1a60 ++#define PCIE_RC_RTSTA_OFF 0x1a14 ++#define PCIE_DEBUG_CTRL_OFF 0x1a60 + #define PCIE_DEBUG_SOFT_RESET BIT(20) + + struct mvebu_pcie_port; +@@ -296,10 +296,10 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) + * be set to number of SerDes PCIe lanes (1 or 4). If this register is + * not set correctly then link with endpoint card is not established. + */ +- lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); ++ lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP); + lnkcap &= ~PCI_EXP_LNKCAP_MLW; + lnkcap |= (port->is_x4 ? 4 : 1) << 4; +- mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); ++ mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP); + + /* Disable Root Bridge I/O space, memory space and bus mastering. */ + cmd = mvebu_readl(port, PCIE_CMD_OFF); +@@ -690,11 +690,11 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + + switch (reg) { + case PCI_EXP_DEVCAP: +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCAP); + break; + + case PCI_EXP_DEVCTL: +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL); + break; + + case PCI_EXP_LNKCAP: +@@ -704,13 +704,13 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + * Additionally enable Data Link Layer Link Active Reporting + * Capable bit as DL_Active indication is provided too. + */ +- *value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & ++ *value = (mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP) & + ~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC; + break; + + case PCI_EXP_LNKCTL: + /* DL_Active indication is provided via PCIE_STAT_OFF */ +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) | ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL) | + (mvebu_pcie_link_up(port) ? + (PCI_EXP_LNKSTA_DLLLA << 16) : 0); + break; +@@ -748,19 +748,19 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + break; + + case PCI_EXP_RTSTA: +- *value = mvebu_readl(port, PCIE_RC_RTSTA); ++ *value = mvebu_readl(port, PCIE_RC_RTSTA_OFF); + break; + + case PCI_EXP_DEVCAP2: +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2); ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCAP2); + break; + + case PCI_EXP_DEVCTL2: +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL2); + break; + + case PCI_EXP_LNKCTL2: +- *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); ++ *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL2); + break; + + default: +@@ -902,7 +902,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + switch (reg) { + case PCI_EXP_DEVCTL: +- mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); ++ mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL); + break; + + case PCI_EXP_LNKCTL: +@@ -913,7 +913,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + */ + new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; + +- mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); ++ mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL); + /* + * When dropping to Detect via Hot Reset, Disable Link + * or Loopback states, the Link Failure interrupt is not +@@ -953,7 +953,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + case PCI_EXP_RTSTA: + /* +- * PME Status bit in Root Status Register (PCIE_RC_RTSTA) ++ * PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) + * is read-only and can be cleared only by writing 0b to the + * Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So + * clear PME via Interrupt Cause and also set port->pme_pending +@@ -978,11 +978,11 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + break; + + case PCI_EXP_DEVCTL2: +- mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); ++ mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL2); + break; + + case PCI_EXP_LNKCTL2: +- mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); ++ mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL2); + break; + + default: +@@ -1042,7 +1042,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF); + u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); + u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF); +- u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); ++ u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF); + u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); + + bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff); +@@ -1103,7 +1103,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + bridge->subsystem_vendor_id = ssdev_id & 0xffff; + bridge->subsystem_id = ssdev_id >> 16; + bridge->has_pcie = true; +- bridge->pcie_start = PCIE_CAP_PCIEXP; ++ bridge->pcie_start = PCIE_CAP_PCIEXP_OFF; + bridge->data = port; + bridge->ops = &mvebu_pci_bridge_emul_ops; + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0048-PCI-aardvark-Dispose-INTx-irqs-prior-to-removing-INT.patch b/nixos/modules/omnia-kernel-patches/0048-PCI-aardvark-Dispose-INTx-irqs-prior-to-removing-INT.patch new file mode 100644 index 0000000..4ad24e9 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0048-PCI-aardvark-Dispose-INTx-irqs-prior-to-removing-INT.patch @@ -0,0 +1,44 @@ +From 83765ecae23eaebcf1821ee49acf4e600cf0ac78 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Sat, 9 Jul 2022 16:55:54 +0200 +Subject: [PATCH 48/53] PCI: aardvark: Dispose INTx irqs prior to removing INTx + domain +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Documentation for irq_domain_remove() says that all mapping within the +domain must be disposed prior to domain remove. + +Currently INTx irqs are not disposed in pci-aardvark.c device unbind callback +which cause that kernel crashes after unloading driver and trying to read +/sys/kernel/debug/irq/irqs/<num> or /proc/interrupts. + +Fixes: 526a76991b7b ("PCI: aardvark: Implement driver 'remove' function and allow to build it as module") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 4834198cc86b..671d89fd91fc 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -1528,6 +1528,14 @@ static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) + + static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) + { ++ int virq, i; ++ ++ for (i = 0; i < PCI_NUM_INTX; i++) { ++ virq = irq_find_mapping(pcie->irq_domain, i); ++ if (virq > 0) ++ irq_dispose_mapping(virq); ++ } ++ + irq_domain_remove(pcie->irq_domain); + } + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0049-PCI-aardvark-Dispose-bridge-irq-prior-to-removing-br.patch b/nixos/modules/omnia-kernel-patches/0049-PCI-aardvark-Dispose-bridge-irq-prior-to-removing-br.patch new file mode 100644 index 0000000..95519e9 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0049-PCI-aardvark-Dispose-bridge-irq-prior-to-removing-br.patch @@ -0,0 +1,41 @@ +From f771fdb6b6dfeab92087c7e3dbc27794b1066585 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 24 Aug 2022 15:59:49 +0200 +Subject: [PATCH 49/53] PCI: aardvark: Dispose bridge irq prior to removing + bridge domain +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Documentation for irq_domain_remove() says that all mapping within the +domain must be disposed prior to domain remove. + +Currently bridge irq is not disposed in pci-aardvark.c device unbind callback +which cause that kernel crashes after unloading driver and trying to read +/sys/kernel/debug/irq/irqs/<num> or /proc/interrupts. + +Fixes: 815bc3136867 ("PCI: aardvark: Use separate INTA interrupt for emulated root bridge") +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 671d89fd91fc..65cd1095984f 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -1574,6 +1574,11 @@ static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) + + static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) + { ++ int virq; ++ ++ virq = irq_find_mapping(pcie->rp_irq_domain, 0); ++ if (virq > 0) ++ irq_dispose_mapping(virq); + irq_domain_remove(pcie->rp_irq_domain); + } + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0050-PCI-aardvark-Add-support-for-DLLSC-and-hotplug-inter.patch b/nixos/modules/omnia-kernel-patches/0050-PCI-aardvark-Add-support-for-DLLSC-and-hotplug-inter.patch new file mode 100644 index 0000000..0ae4669 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0050-PCI-aardvark-Add-support-for-DLLSC-and-hotplug-inter.patch @@ -0,0 +1,268 @@ +From acd743b13658e7255b6c5da3be2031b800872190 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 31 Aug 2022 15:55:46 +0200 +Subject: [PATCH 50/53] PCI: aardvark: Add support for DLLSC and hotplug + interrupt +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for Data Link Layer State Change in the emulated slot +registers and hotplug interrupt via the emulated root bridge. + +This is mainly useful for when an error causes link down event. With +this change, drivers can try recovery. + +Link down state change can be implemented because Aardvark supports Link +Down event interrupt. Use it for signaling that Data Link Layer Link is +not active anymore via Hot-Plug Interrupt on emulated root bridge. + +Link up interrupt is not available on Aardvark, but we check for whether +link is up in the advk_pcie_link_up() function. By triggering Hot-Plug +Interrupt from this function we achieve Link up event, so long as the +function is called (which it is after probe and when rescanning). +Although it is not ideal, it is better than nothing. + +Since advk_pcie_link_up() is not called from interrupt handler, we +cannot call generic_handle_domain_irq() from it directly. Instead create +a TIMER_IRQSAFE timer and trigger it from advk_pcie_link_up(). + +(We haven't been able to find any documentation for a Link Up interrupt + on Aardvark, but it is possible there is one, in some undocumented + register. If we manage to find this information, this can be + rewritten.) + +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/controller/Kconfig | 3 + + drivers/pci/controller/pci-aardvark.c | 101 ++++++++++++++++++++++++-- + 2 files changed, 99 insertions(+), 5 deletions(-) + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index 8da2efdc5177..639a68e65363 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -24,6 +24,9 @@ config PCI_AARDVARK + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + select PCI_BRIDGE_EMUL ++ select PCIEPORTBUS ++ select HOTPLUG_PCI ++ select HOTPLUG_PCI_PCIE + help + Add support for Aardvark 64bit PCIe Host Controller. This + controller is part of the South Bridge of the Marvel Armada +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 65cd1095984f..9a7db62982a6 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -25,6 +25,7 @@ + #include <linux/of_address.h> + #include <linux/of_gpio.h> + #include <linux/of_pci.h> ++#include <linux/timer.h> + + #include "../pci.h" + #include "../pci-bridge-emul.h" +@@ -100,6 +101,7 @@ + #define PCIE_MSG_PM_PME_MASK BIT(7) + #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) + #define PCIE_ISR0_MSI_INT_PENDING BIT(24) ++#define PCIE_ISR0_LINK_DOWN BIT(1) + #define PCIE_ISR0_CORR_ERR BIT(11) + #define PCIE_ISR0_NFAT_ERR BIT(12) + #define PCIE_ISR0_FAT_ERR BIT(13) +@@ -284,6 +286,8 @@ struct advk_pcie { + DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); + struct mutex msi_used_lock; + int link_gen; ++ bool link_was_up; ++ struct timer_list link_irq_timer; + struct pci_bridge_emul bridge; + struct gpio_desc *reset_gpio; + struct phy *phy; +@@ -313,7 +317,24 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) + { + /* check if LTSSM is in normal operation - some L* state */ + u8 ltssm_state = advk_pcie_ltssm_state(pcie); +- return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; ++ bool link_is_up; ++ u16 slotsta; ++ ++ link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; ++ ++ if (link_is_up && !pcie->link_was_up) { ++ dev_info(&pcie->pdev->dev, "link up\n"); ++ ++ pcie->link_was_up = true; ++ ++ slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); ++ slotsta |= PCI_EXP_SLTSTA_DLLSC; ++ pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); ++ ++ mod_timer(&pcie->link_irq_timer, jiffies + 1); ++ } ++ ++ return link_is_up; + } + + static inline bool advk_pcie_link_active(struct advk_pcie *pcie) +@@ -442,8 +463,6 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) + ret = advk_pcie_wait_for_link(pcie); + if (ret < 0) + dev_err(dev, "link never came up\n"); +- else +- dev_info(dev, "link up\n"); + } + + /* +@@ -592,6 +611,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) + reg &= ~PCIE_ISR0_MSI_INT_PENDING; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + ++ /* Unmask Link Down interrupt */ ++ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); ++ reg &= ~PCIE_ISR0_LINK_DOWN; ++ advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); ++ + /* Unmask PME interrupt for processing of PME requester */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_MSG_PM_PME_MASK; +@@ -918,6 +942,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + advk_pcie_wait_for_retrain(pcie); + break; + ++ case PCI_EXP_SLTCTL: { ++ u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); ++ /* Only emulation of HPIE and DLLSCE bits is provided */ ++ slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; ++ bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); ++ break; ++ } ++ + case PCI_EXP_RTCTL: { + u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); + /* Only emulation of PMEIE and CRSSVE bits is provided */ +@@ -1035,6 +1067,7 @@ static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { + static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) + { + struct pci_bridge_emul *bridge = &pcie->bridge; ++ u32 slotcap; + + bridge->conf.vendor = + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); +@@ -1061,6 +1094,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) + bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); + + /* ++ * Mark bridge as Hot Plug Capable since this is the way how to enable ++ * delivering of Data Link Layer State Change interrupts. ++ * ++ * Set No Command Completed Support because bridge does not support ++ * Command Completed Interrupt. Every command is executed immediately ++ * without any delay. ++ * + * Set Presence Detect State bit permanently since there is no support + * for unplugging the card nor detecting whether it is plugged. (If a + * platform exists in the future that supports it, via a GPIO for +@@ -1070,8 +1110,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) + * value is reserved for ports within the same silicon as Root Port + * which is not our case. + */ +- bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, +- 1)); ++ slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | ++ FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); ++ bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); + bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); + + /* Indicates supports for Completion Retry Status */ +@@ -1582,6 +1623,24 @@ static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) + irq_domain_remove(pcie->rp_irq_domain); + } + ++static void advk_pcie_link_irq_handler(struct timer_list *timer) ++{ ++ struct advk_pcie *pcie = from_timer(pcie, timer, link_irq_timer); ++ u16 slotctl; ++ ++ slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); ++ if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || ++ !(slotctl & PCI_EXP_SLTCTL_HPIE)) ++ return; ++ ++ /* ++ * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe ++ * interrupt 0 ++ */ ++ if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) ++ dev_err_ratelimited(&pcie->pdev->dev, "unhandled HP IRQ\n"); ++} ++ + static void advk_pcie_handle_pme(struct advk_pcie *pcie) + { + u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; +@@ -1633,6 +1692,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) + { + u32 isr0_val, isr0_mask, isr0_status; + u32 isr1_val, isr1_mask, isr1_status; ++ u16 slotsta; + int i; + + isr0_val = advk_readl(pcie, PCIE_ISR0_REG); +@@ -1659,6 +1719,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); + } + ++ /* Process Link Down interrupt as HP IRQ */ ++ if (isr0_status & PCIE_ISR0_LINK_DOWN) { ++ advk_writel(pcie, PCIE_ISR0_LINK_DOWN, PCIE_ISR0_REG); ++ ++ dev_info(&pcie->pdev->dev, "link down\n"); ++ ++ pcie->link_was_up = false; ++ ++ slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); ++ slotsta |= PCI_EXP_SLTSTA_DLLSC; ++ pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); ++ ++ /* ++ * Deactivate timer and call advk_pcie_link_irq_handler() ++ * function directly as we are in the interrupt context. ++ */ ++ del_timer_sync(&pcie->link_irq_timer); ++ advk_pcie_link_irq_handler(&pcie->link_irq_timer); ++ } ++ + /* Process MSI interrupts */ + if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) + advk_pcie_handle_msi(pcie); +@@ -1895,6 +1975,14 @@ static int advk_pcie_probe(struct platform_device *pdev) + if (ret) + return ret; + ++ /* ++ * generic_handle_domain_irq() expects local IRQs to be disabled since ++ * normally it is called from interrupt context, so use TIMER_IRQSAFE ++ * flag for this link_irq_timer. ++ */ ++ timer_setup(&pcie->link_irq_timer, advk_pcie_link_irq_handler, ++ TIMER_IRQSAFE); ++ + advk_pcie_setup_hw(pcie); + + ret = advk_sw_pci_bridge_init(pcie); +@@ -1983,6 +2071,9 @@ static int advk_pcie_remove(struct platform_device *pdev) + advk_pcie_remove_msi_irq_domain(pcie); + advk_pcie_remove_irq_domain(pcie); + ++ /* Deactivate link event timer */ ++ del_timer_sync(&pcie->link_irq_timer); ++ + /* Free config space for emulated root bridge */ + pci_bridge_emul_cleanup(&pcie->bridge); + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0051-PCI-aardvark-Send-Set_Slot_Power_Limit-message.patch b/nixos/modules/omnia-kernel-patches/0051-PCI-aardvark-Send-Set_Slot_Power_Limit-message.patch new file mode 100644 index 0000000..c565c7f --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0051-PCI-aardvark-Send-Set_Slot_Power_Limit-message.patch @@ -0,0 +1,148 @@ +From 2010d62095990f6074350d37483579f4089b4239 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Wed, 31 Aug 2022 15:57:01 +0200 +Subject: [PATCH 51/53] PCI: aardvark: Send Set_Slot_Power_Limit message +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Emulate Slot PowerLimit Scale and Value bits in the Slot Capabilities +register of the emulated bridge and if slot power limit value is +defined, send that Set_Slot_Power_Limit message via Message Generation +Control Register in Link Up handler on link up event. + +Slot power limit value is read from device-tree property +'slot-power-limit-milliwatt'. If this property is not specified, we +treat it as "Slot Capabilities register has not yet been initialized". + +According to PCIe Base specification 3.0, when transitioning from a +non-DL_Up Status to a DL_Up Status, the Port must initiate the +transmission of a Set_Slot_Power_Limit Message to the other component +on the Link to convey the value programmed in the Slot Power Limit +Scale and Value fields of the Slot Capabilities register. This +transmission is optional if the Slot Capabilities register has not +yet been initialized. + +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 51 ++++++++++++++++++++++++--- + 1 file changed, 47 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 9a7db62982a6..3a7aece3eff2 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -213,6 +213,11 @@ enum { + }; + + #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) ++#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) ++#define SEND_SET_SLOT_POWER_LIMIT BIT(13) ++#define SEND_PME_TURN_OFF BIT(14) ++#define SLOT_POWER_LIMIT_DATA_SHIFT 16 ++#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) + + /* PCIe core controller registers */ + #define CTRL_CORE_BASE_ADDR 0x18000 +@@ -285,6 +290,8 @@ struct advk_pcie { + raw_spinlock_t msi_irq_lock; + DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); + struct mutex msi_used_lock; ++ u8 slot_power_limit_value; ++ u8 slot_power_limit_scale; + int link_gen; + bool link_was_up; + struct timer_list link_irq_timer; +@@ -317,8 +324,9 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) + { + /* check if LTSSM is in normal operation - some L* state */ + u8 ltssm_state = advk_pcie_ltssm_state(pcie); ++ u16 slotsta, slotctl; ++ u32 slotpwr, val; + bool link_is_up; +- u16 slotsta; + + link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + +@@ -332,6 +340,27 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + mod_timer(&pcie->link_irq_timer, jiffies + 1); ++ ++ /* ++ * According to PCIe Base specification 3.0, when transitioning ++ * from a non-DL_Up Status to a DL_Up Status, the Port must ++ * initiate the transmission of a Set_Slot_Power_Limit Message ++ * to the other component on the Link to convey the value ++ * programmed in the Slot Power Limit Scale and Value fields of ++ * the Slot Capabilities register. This transmission is optional ++ * if the Slot Capabilities register has not yet been ++ * initialized. ++ */ ++ slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); ++ slotpwr = FIELD_GET(PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS, ++ le32_to_cpu(pcie->bridge.pcie_conf.slotcap)); ++ if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { ++ val = advk_readl(pcie, PME_MSG_GEN_CTRL); ++ val &= ~SLOT_POWER_LIMIT_DATA_MASK; ++ val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; ++ val |= SEND_SET_SLOT_POWER_LIMIT; ++ advk_writel(pcie, val, PME_MSG_GEN_CTRL); ++ } + } + + return link_is_up; +@@ -944,8 +973,9 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); +- /* Only emulation of HPIE and DLLSCE bits is provided */ +- slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; ++ /* Only emulation of HPIE, DLLSCE and ASPLD bits is provided */ ++ slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE | ++ PCI_EXP_SLTCTL_ASPL_DISABLE; + bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); + break; + } +@@ -1109,9 +1139,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) + * Set physical slot number to 1 since there is only one port and zero + * value is reserved for ports within the same silicon as Root Port + * which is not our case. ++ * ++ * Set slot power limit. + */ + slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | +- FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); ++ FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1) | ++ FIELD_PREP(PCI_EXP_SLTCAP_SPLV, pcie->slot_power_limit_value) | ++ FIELD_PREP(PCI_EXP_SLTCAP_SPLS, pcie->slot_power_limit_scale); + bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); + bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); + +@@ -1851,6 +1885,7 @@ static int advk_pcie_probe(struct platform_device *pdev) + struct advk_pcie *pcie; + struct pci_host_bridge *bridge; + struct resource_entry *entry; ++ u32 slot_power_limit; + int ret, irq; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); +@@ -1971,6 +2006,14 @@ static int advk_pcie_probe(struct platform_device *pdev) + else + pcie->link_gen = ret; + ++ slot_power_limit = of_pci_get_slot_power_limit(dev->of_node, ++ &pcie->slot_power_limit_value, ++ &pcie->slot_power_limit_scale); ++ if (slot_power_limit) ++ dev_info(dev, "Slot Power Limit: %u.%uW\n", ++ slot_power_limit / 1000, ++ (slot_power_limit / 100) % 10); ++ + ret = advk_pcie_setup_phy(pcie); + if (ret) + return ret; +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0052-PCI-aardvark-Add-clock-support.patch b/nixos/modules/omnia-kernel-patches/0052-PCI-aardvark-Add-clock-support.patch new file mode 100644 index 0000000..5cc802f --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0052-PCI-aardvark-Add-clock-support.patch @@ -0,0 +1,93 @@ +From 01c7f950dcbee2d007e4442d0fa0cf3d5933bb50 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal <miquel.raynal@bootlin.com> +Date: Wed, 31 Aug 2022 15:59:39 +0200 +Subject: [PATCH 52/53] PCI: aardvark: Add clock support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The IP relies on a gated clock. When we will add S2RAM support, this +clock will need to be resumed before any PCIe registers are +accessed. Add support for this clock. + +Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 32 +++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 3a7aece3eff2..9f94c7a1951a 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -9,6 +9,7 @@ + */ + + #include <linux/bitfield.h> ++#include <linux/clk.h> + #include <linux/delay.h> + #include <linux/gpio/consumer.h> + #include <linux/interrupt.h> +@@ -297,6 +298,7 @@ struct advk_pcie { + struct timer_list link_irq_timer; + struct pci_bridge_emul bridge; + struct gpio_desc *reset_gpio; ++ struct clk *clk; + struct phy *phy; + }; + +@@ -1823,6 +1825,29 @@ static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + return of_irq_parse_and_map_pci(dev, slot, pin); + } + ++static int advk_pcie_setup_clk(struct advk_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ int ret; ++ ++ pcie->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) ++ return PTR_ERR(pcie->clk); ++ ++ /* Old bindings miss the clock handle */ ++ if (IS_ERR(pcie->clk)) { ++ dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); ++ pcie->clk = NULL; ++ return 0; ++ } ++ ++ ret = clk_prepare_enable(pcie->clk); ++ if (ret) ++ dev_err(dev, "Clock initialization failed (%d)\n", ret); ++ ++ return ret; ++} ++ + static void advk_pcie_disable_phy(struct advk_pcie *pcie) + { + phy_power_off(pcie->phy); +@@ -2014,6 +2039,10 @@ static int advk_pcie_probe(struct platform_device *pdev) + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + ++ ret = advk_pcie_setup_clk(pcie); ++ if (ret) ++ return ret; ++ + ret = advk_pcie_setup_phy(pcie); + if (ret) + return ret; +@@ -2136,6 +2165,9 @@ static int advk_pcie_remove(struct platform_device *pdev) + /* Disable phy */ + advk_pcie_disable_phy(pcie); + ++ /* Disable clock */ ++ clk_disable_unprepare(pcie->clk); ++ + return 0; + } + +-- +2.37.3 + diff --git a/nixos/modules/omnia-kernel-patches/0053-PCI-aardvark-Add-suspend-to-RAM-support.patch b/nixos/modules/omnia-kernel-patches/0053-PCI-aardvark-Add-suspend-to-RAM-support.patch new file mode 100644 index 0000000..059f06d --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0053-PCI-aardvark-Add-suspend-to-RAM-support.patch @@ -0,0 +1,74 @@ +From 90716424fc80b3176134eed02fe4664c404a3847 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal <miquel.raynal@bootlin.com> +Date: Wed, 31 Aug 2022 16:07:27 +0200 +Subject: [PATCH 53/53] PCI: aardvark: Add suspend to RAM support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add suspend and resume callbacks. We need to use the NOIRQ variants to +ensure the controller's IRQ handlers are not run during suspend() / +resume(), which could cause races. + +Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 34 +++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 9f94c7a1951a..516bc9f818c0 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -1904,6 +1904,39 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie) + return ret; + } + ++static int advk_pcie_suspend(struct device *dev) ++{ ++ struct advk_pcie *pcie = dev_get_drvdata(dev); ++ ++ advk_pcie_disable_phy(pcie); ++ ++ clk_disable_unprepare(pcie->clk); ++ ++ return 0; ++} ++ ++static int advk_pcie_resume(struct device *dev) ++{ ++ struct advk_pcie *pcie = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(pcie->clk); ++ if (ret) ++ return ret; ++ ++ ret = advk_pcie_enable_phy(pcie); ++ if (ret) ++ return ret; ++ ++ advk_pcie_setup_hw(pcie); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops advk_pcie_dev_pm_ops = { ++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(advk_pcie_suspend, advk_pcie_resume) ++}; ++ + static int advk_pcie_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -2181,6 +2214,7 @@ static struct platform_driver advk_pcie_driver = { + .driver = { + .name = "advk-pcie", + .of_match_table = advk_pcie_of_match_table, ++ .pm = &advk_pcie_dev_pm_ops, + }, + .probe = advk_pcie_probe, + .remove = advk_pcie_remove, +-- +2.37.3 + |