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From 40e275d7eba809c9be431eb881c2ef1086747e0b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Mon, 18 Apr 2022 00:40:05 +0200
Subject: [PATCH 41/53] ARM: dts: armada-385.dtsi: Add definitions for PCIe
error interrupts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
PCIe error interrupt is reported by MPIC SoC Error IRQ controller.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/arm/boot/dts/armada-385.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index be8d607c59b2..d603de5aa574 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -69,8 +69,9 @@ pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intx", "error";
+ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <&soc_err 4>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
@@ -97,8 +98,9 @@ pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intx", "error";
+ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <&soc_err 5>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
@@ -125,8 +127,9 @@ pcie3: pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intx", "error";
+ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <&soc_err 15>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
@@ -156,8 +159,9 @@ pcie4: pcie@4,0 {
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intx", "error";
+ interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <&soc_err 16>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
--
2.37.3
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